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Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs
Citation
Royer del Barrio, Pablo and Sánchez Marcos, Miguel Ángel and López Vallejo, Marisa and López Barrio, Carlos Alberto (2011). Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs. In: "26th Conference on Design of Circuits and Integrated Systems", 16/11/2011 - 18/11/2011, Albufeira, Portugal.
Description
| Title: | Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs |
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| Author/s: |
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| Item Type: | Presentation at Congress or Conference (Article) |
| Event Title: | 26th Conference on Design of Circuits and Integrated Systems |
| Event Dates: | 16/11/2011 - 18/11/2011 |
| Event Location: | Albufeira, Portugal |
| Title of Book: | Proceedings of 26th Conference on Design of Circuits and Integrated Systems |
| Date: | 2011 |
| Subjects: | |
| Faculty: | E.T.S.I. Telecomunicación (UPM) |
| Department: | Ingeniería Electrónica |
| Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
Abstract
Linear regression is a technique widely used in digital signal processing. It consists on finding the linear function that better fits a given set of samples. This paper proposes different hardware architectures for the implementation of the linear regression method on FPGAs, specially targeting area restrictive systems. It saves area at the cost of constraining the lengths of the input signal to some fixed values. We have implemented the proposed scheme in an Automatic Modulation Classifier, meeting the hard real-time constraints this kind of systems have.
More information
| Item ID: | 12192 |
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| DC Identifier: | http://oa.upm.es/12192/ |
| OAI Identifier: | oai:oa.upm.es:12192 |
| Official URL: | http://paginas.fe.up.pt/~dcis2011/ |
| Deposited by: | Memoria Investigacion |
| Deposited on: | 30 Aug 2012 10:54 |
| Last Modified: | 21 Apr 2016 11:23 |
