Wake up Radio Architecture for Wireless Sensor Networks Using an Ultra Low Power FPGA

Roselló Gómez-Lobo, Víctor Julián and Portilla Berrueco, Jorge and Riesgo Alcaide, Teresa (2011). Wake up Radio Architecture for Wireless Sensor Networks Using an Ultra Low Power FPGA. In: "DCIS 2011 26th Confenrence on Design of Circuits and Integrated Systems", 16/11/2011 - 18/11/2011, Albufeira, Portugal.

Description

Title: Wake up Radio Architecture for Wireless Sensor Networks Using an Ultra Low Power FPGA
Author/s:
  • Roselló Gómez-Lobo, Víctor Julián
  • Portilla Berrueco, Jorge
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: DCIS 2011 26th Confenrence on Design of Circuits and Integrated Systems
Event Dates: 16/11/2011 - 18/11/2011
Event Location: Albufeira, Portugal
Title of Book: Proceedings of DCIS 2011 26th Confenrence on Design of Circuits and Integrated Systems
Date: 2011
Subjects:
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

In this paper an implementation of a Wake up Radio(WuR) with addressing capabilities based on an ultra low power FPGA for ultra low energy Wireless Sensor Networks (WSNs) is proposed. The main goal is to evaluate the utilization of very low power configurable devices to take advantage of their speed, flexibility and low power consumption instead of the traditional approaches based on ASICs or microcontrollers, for communication frame decoding and communication data control.

More information

Item ID: 12207
DC Identifier: http://oa.upm.es/12207/
OAI Identifier: oai:oa.upm.es:12207
Official URL: http://paginas.fe.up.pt/~dcis2011/index.html
Deposited by: Memoria Investigacion
Deposited on: 30 Aug 2012 07:37
Last Modified: 21 Apr 2016 11:25
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