A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

He, Wei; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2011). A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. En: "2011 International Conference on Reconfigurable Computing and FPGAs, RECONFIG '11", 30/11/2011 - 02/12/2011, Cancú, México. ISBN 978-0-7695-4551-6.

Descripción

Título: A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations
Autor/es:
  • He, Wei
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 2011 International Conference on Reconfigurable Computing and FPGAs, RECONFIG '11
Fechas del Evento: 30/11/2011 - 02/12/2011
Lugar del Evento: Cancú, México
Título del Libro: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, RECONFIG '11
Fecha: 2011
ISBN: 978-0-7695-4551-6
Materias:
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this proposal is that the EPE can be effectively prevented by using a synchronized non regular precharge network, which maintains identical routing between the original and mirror parts, where costs and design complexity compared with previous EPE-resistant countermeasures are reduced, while security level is not sacrificed. Another advantage for our Precharge Absorbed(PA) - DPL method is that its Dual-Core style (independent architecture for true and false parts) could be generated using partial reconfiguration. This helps to get a dynamic security protection with better energy planning. That means system only keeps the true part which fulfills the normal en/decryption task in low security level, and reconfigures the false parts once high security level is required. A relatively limited clock speed is a compromise, since signal propagation is restricted to a portion of the clock period. In this paper, we explain the principles of PA-DPL and provide the guidelines to design this structure. We experimentally validate our methods in a minimized AES co-processor on Xilinx Virtex-5 board using electromagnetic (EM) attacks.

Más información

ID de Registro: 12223
Identificador DC: http://oa.upm.es/12223/
Identificador OAI: oai:oa.upm.es:12223
URL Oficial: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6128580
Depositado por: Memoria Investigacion
Depositado el: 28 Ago 2012 11:32
Ultima Modificación: 21 Abr 2016 11:26
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