A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems

Otero Marnotes, Andres and Salvador Perea, Rubén and Mora, Javier and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Sekanina, Lukás (2011). A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems. In: "2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 06/06/2011 - 09/06/2011, San Diego (California, USA). ISBN 978-1-4577-0598-4. pp. 336-343.

Description

Title: A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems
Author/s:
  • Otero Marnotes, Andres
  • Salvador Perea, Rubén
  • Mora, Javier
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
  • Sekanina, Lukás
Item Type: Presentation at Congress or Conference (Article)
Event Title: 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Event Dates: 06/06/2011 - 09/06/2011
Event Location: San Diego (California, USA)
Title of Book: Proceedings of 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Date: 2011
ISBN: 978-1-4577-0598-4
Subjects:
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) feature allow the implementation of complex, yet flexible, hardware systems. Combining this flexibility with evolvable hardware techniques, real adaptive systems, able to reconfigure themselves according to environmental changes, can be envisaged. In this paper, a highly regular and modular architecture combined with a fast reconfiguration mechanism is proposed, allowing the introduction of dynamic and partial reconfiguration in the evolvable hardware loop. Results and use case show that, following this approach, evolvable processing IP Cores can be built, providing intensive data processing capabilities, improving data and delay overheads with respect to previous proposals. Results also show that, in the worst case (maximum mutation rate), average reconfiguration time is 5 times lower than evaluation time.

More information

Item ID: 12899
DC Identifier: http://oa.upm.es/12899/
OAI Identifier: oai:oa.upm.es:12899
Official URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5963956
Deposited by: Memoria Investigacion
Deposited on: 08 Nov 2012 11:53
Last Modified: 21 Apr 2016 12:13
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