Bio-inspired FPGA Architecture for Self-Calibration of an Image Compression Core based on Wavelet Transforms in Embedded Systems

Salvador Perea, Rubén; Vidal, Alberto; Moreno González, Félix Antonio; Riesgo Alcaide, Teresa y Sekanina, Lukás (2011). Bio-inspired FPGA Architecture for Self-Calibration of an Image Compression Core based on Wavelet Transforms in Embedded Systems. En: "VLSI Circuits and Systems V", 18/04/2011 - 20/04/2011, Praga, República Checa. ISBN 9780819486561. pp. 1-13.

Descripción

Título: Bio-inspired FPGA Architecture for Self-Calibration of an Image Compression Core based on Wavelet Transforms in Embedded Systems
Autor/es:
  • Salvador Perea, Rubén
  • Vidal, Alberto
  • Moreno González, Félix Antonio
  • Riesgo Alcaide, Teresa
  • Sekanina, Lukás
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: VLSI Circuits and Systems V
Fechas del Evento: 18/04/2011 - 20/04/2011
Lugar del Evento: Praga, República Checa
Título del Libro: Proceedings of SPIE VLSI Circuits and Systems V
Fecha: 2011
ISBN: 9780819486561
Volumen: 8067
Materias:
Escuela: E.U.I.T. Telecomunicación (UPM) [antigua denominación]
Departamento: Sistemas Electrónicos y de Control [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

A generic bio-inspired adaptive architecture for image compression suitable to be implemented in embedded systems is presented. The architecture allows the system to be tuned during its calibration phase. An evolutionary algorithm is responsible of making the system evolve towards the required performance. A prototype has been implemented in a Xilinx Virtex-5 FPGA featuring an adaptive wavelet transform core directed at improving image compression for specific types of images. An Evolution Strategy has been chosen as the search algorithm and its typical genetic operators adapted to allow for a hardware friendly implementation. HW/SW partitioning issues are also considered after a high level description of the algorithm is profiled which validates the proposed resource allocation in the device fabric. To check the robustness of the system and its adaptation capabilities, different types of images have been selected as validation patterns. A direct application of such a system is its deployment in an unknown environment during design time, letting the calibration phase adjust the system parameters so that it performs efcient image compression. Also, this prototype implementation may serve as an accelerator for the automatic design of evolved transform coefficients which are later on synthesized and implemented in a non-adaptive system in the final implementation device, whether it is a HW or SW based computing device. The architecture has been built in a modular way so that it can be easily extended to adapt other types of image processing cores. Details on this pluggable component point of view are also given in the paper.

Más información

ID de Registro: 13030
Identificador DC: http://oa.upm.es/13030/
Identificador OAI: oai:oa.upm.es:13030
URL Oficial: http://spie.org/x648.html?product_id=871765
Depositado por: Memoria Investigacion
Depositado el: 11 Dic 2012 08:26
Ultima Modificación: 23 Feb 2017 17:36
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