Suitability of artificial neural networks for designing LoC circuits

Gomez Canaval, Sandra Maria and Castellanos Peñuela, Juan Bautista and Moreno Navas, David (2011). Suitability of artificial neural networks for designing LoC circuits. In: "11th International Work-Conference on Artificial Neural Networks, IWANN 2011", June 8-10, 2011, Torremolinos-Málaga, España. ISBN 978-3-642-21500-1.

Description

Title: Suitability of artificial neural networks for designing LoC circuits
Author/s:
  • Gomez Canaval, Sandra Maria
  • Castellanos Peñuela, Juan Bautista
  • Moreno Navas, David
Item Type: Presentation at Congress or Conference (Article)
Event Title: 11th International Work-Conference on Artificial Neural Networks, IWANN 2011
Event Dates: June 8-10, 2011
Event Location: Torremolinos-Málaga, España
Title of Book: Advances in Computational Intelligence
Date: 2011
ISBN: 978-3-642-21500-1
Volume: 6691
Subjects:
Freetext Keywords: LoC, Lab-on-a-Chip, MOR, Microfluidic devices, Nanofluidic devices, Artificial neural networks, Dispositivos microfluídicos, Dispositivos nanofluídicos, Redes neuronales artificiales.
Faculty: Facultad de Informática (UPM)
Department: Inteligencia Artificial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

he simulation of complex LoC (Lab-on-a-Chip) devices is a process that requires solving computationally expensive partial differential equations. An interesting alternative uses artificial neural networks for creating computationally feasible models based on MOR techniques. This paper proposes an approach that uses artificial neural networks for designing LoC components considering the artificial neural network topology as an isomorphism of the LoC device topology. The parameters of the trained neural networks are based on equations for modeling microfluidic circuits, analogous to electronic circuits. The neural networks have been trained to behave like AND, OR, Inverter gates. The parameters of the trained neural networks represent the features of LoC devices that behave as the aforementioned gates. This would mean that LoC devices universally compute.

More information

Item ID: 19303
DC Identifier: http://oa.upm.es/19303/
OAI Identifier: oai:oa.upm.es:19303
Official URL: http://link.springer.com/chapter/10.1007%2F978-3-642-21501-8_38
Deposited by: Memoria Investigacion
Deposited on: 25 Sep 2013 16:56
Last Modified: 21 Apr 2016 17:33
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