Implementing FFT-based digital channelized receivers on FPGA platforms

Sánchez Marcos, Miguel Ángel and Garrido Gálvez, Mario and López Vallejo, Marisa and Grajal de la Fuente, Jesús (2008). Implementing FFT-based digital channelized receivers on FPGA platforms. "IEEE Transactions on Aerospace and Electronic Systems", v. 44 (n. 4); pp. 1567-1585. ISSN 0018-9251.

Description

Title: Implementing FFT-based digital channelized receivers on FPGA platforms
Author/s:
  • Sánchez Marcos, Miguel Ángel
  • Garrido Gálvez, Mario
  • López Vallejo, Marisa
  • Grajal de la Fuente, Jesús
Item Type: Article
Título de Revista/Publicación: IEEE Transactions on Aerospace and Electronic Systems
Date: October 2008
Volume: 44
Subjects:
Freetext Keywords: FPGA platforms broadband digital channelized receivers fast Fourier transform pipelined architectures feedback architectures feedforward architectures field-programmable gate array platforms monobit FFT algorithm signal processing systems
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - Non commercial - Share

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Abstract

This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.

More information

Item ID: 2047
DC Identifier: http://oa.upm.es/2047/
OAI Identifier: oai:oa.upm.es:2047
Deposited by: Memoria Investigacion
Deposited on: 11 Jan 2010 09:19
Last Modified: 20 Apr 2016 11:50
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