Implementing FFT-based digital channelized receivers on FPGA platforms

Sánchez Marcos, Miguel Ángel and Garrido Gálvez, Mario and López Vallejo, Marisa and Grajal de la Fuente, Jesús (2008). Implementing FFT-based digital channelized receivers on FPGA platforms. "IEEE Transactions on Aerospace and Electronic Systems", v. 44 (n. 4); pp. 1567-1585. ISSN 0018-9251.

Ver estadísticas de este documento (sólo accesible desde la red de la UPM)

Title:Implementing FFT-based digital channelized receivers on FPGA platforms
Authors/Creators:
Creators NameCreators email (if known)
Sánchez Marcos, Miguel ÁngelUNSPECIFIED
Garrido Gálvez, MarioUNSPECIFIED
López Vallejo, MarisaUNSPECIFIED
Grajal de la Fuente, JesúsUNSPECIFIED
Item Type:Article
Publisher:IEEE
Título de Revista/Publicación:IEEE Transactions on Aerospace and Electronic Systems
Date:October 2008
Volume:44
Number:4
Department:Electronic Engineering
Faculty:E.T.S.I. Telecomunicación (UPM)
Subjects:Telecommunications
Electronics
Mathematics
Freetext Keywords:FPGA platforms broadband digital channelized receivers fast Fourier transform pipelined architectures feedback architectures feedforward architectures field-programmable gate array platforms monobit FFT algorithm signal processing systems
Creative Commons Licenses:Recognition - Non commercial - Share

Full text

[img]
Preview
PDF - Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader 2MB - Idioma: English

Abstract

This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.

Item ID:2047
Deposited by: Memoria Investigacion
Deposited on:11 Jan 2010 09:19
Last Modified:22 Sep 2014 10:02

Repository Staff Only: Edit this record

  • Open Access
  • Sherpa-Romeo
    Check whether the anglo-saxon journal in which you have published an article allows you to also publish it under open access.
  • Dulcinea
    Check whether the spanish journal in which you have published an article allows you to also publish it under open access.
  • Recolecta