Sánchez Marcos, Miguel Ángel and Garrido Gálvez, Mario and López Vallejo, Marisa and Grajal de la Fuente, Jesús (2008). Implementing FFT-based digital channelized receivers on FPGA platforms. "IEEE Transactions on Aerospace and Electronic Systems", v. 44 (n. 4); pp. 1567-1585 . ISSN 0018-9251.Ver estadisticas de descargas para este eprint (solo desde ordenadores de la UPM)
|Title:||Implementing FFT-based digital channelized receivers on FPGA platforms|
|Journal/Publication Title:||IEEE Transactions on Aerospace and Electronic Systems|
|Faculty:||E.T.S.I. Telecomunicación (UPM)|
|Creative Commons Licenses:||Recognition - Non commercial - Share|
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This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.
|Freetext Keywords:||FPGA platforms broadband digital channelized receivers fast Fourier transform pipelined architectures feedback architectures feedforward architectures field-programmable gate array platforms monobit FFT algorithm signal processing systems|
|Deposited by:||Memoria Investigacion|
|Deposited on:||11 Jan 2010 10:19|
|Last Modified:||02 Jan 2013 18:41|
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