A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation

Gomez Osuna, Carlos; Sánchez Marcos, Miguel Ángel; Ituero Herrero, Pablo y López Vallejo, Marisa (2012). A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation. En: "19th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012", 10/12/2012 - 13/12/2012, Sevilla. ISBN 978-1-4673-1259-2. pp. 765-768. https://doi.org/10.1109/ICECS.2012.6463547.

Descripción

Título: A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation
Autor/es:
  • Gomez Osuna, Carlos
  • Sánchez Marcos, Miguel Ángel
  • Ituero Herrero, Pablo
  • López Vallejo, Marisa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012
Fechas del Evento: 10/12/2012 - 13/12/2012
Lugar del Evento: Sevilla
Título del Libro: Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012
Fecha: Diciembre 2012
ISBN: 978-1-4673-1259-2
Materias:
Palabras Clave Informales: CMOS, FPGA, Monitoring, On-Chip, aging, dynamic adaptation leakage, temperature, variability
Escuela: E.T.S.I. Telecomunicación (UPM)
Departamento: Ingeniería Electrónica
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Variabilities associated with CMOS evolution affect the yield and performance of current digital designs. FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues. Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network. This infrastructure, through adequate use of configuration and automation tools, is able to obtain relevant data along the life cycle of an FPGA. This is realised at a very reduced cost, not only in terms of area or other limited resources, but also regarding the design effort required to define and deploy the measuring infrastructure. Our proposal has been validated by measuring inter-die and intra-die variability in different FPGA families.

Más información

ID de Registro: 20500
Identificador DC: http://oa.upm.es/20500/
Identificador OAI: oai:oa.upm.es:20500
Identificador DOI: 10.1109/ICECS.2012.6463547
URL Oficial: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6463547
Depositado por: Memoria Investigacion
Depositado el: 07 Oct 2013 16:05
Ultima Modificación: 21 Abr 2016 23:20
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