A hardware in the loop design methodology for FPGA system and its application to complex functions

Liang, Guixuan and He, Danping and Portilla Berrueco, Jorge and Riesgo Alcaide, Teresa (2012). A hardware in the loop design methodology for FPGA system and its application to complex functions. In: "Proceedings of VLSI, Design, Automation and Test (VLSI-DAT)", 23/04/2012 - 25/04/2012, Hsinchu (Taiwan). ISBN 978-1-4577-2080-2. pp. 1-6.

Description

Title: A hardware in the loop design methodology for FPGA system and its application to complex functions
Author/s:
  • Liang, Guixuan
  • He, Danping
  • Portilla Berrueco, Jorge
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: Proceedings of VLSI, Design, Automation and Test (VLSI-DAT)
Event Dates: 23/04/2012 - 25/04/2012
Event Location: Hsinchu (Taiwan)
Title of Book: VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
Date: 2012
ISBN: 978-1-4577-2080-2
Subjects:
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Otro
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

In this work, a unified algorithm-architecture-circuit co-design environment for complex FPGA system development is presented. The main objective is to find an efficient methodology for designing a configurable optimized FPGA system by using as few efforts as possible in verification stage, so as to speed up the development period. A proposed high performance FFT/iFFT processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB) system design process is given as an example to demonstrate the proposed methodology. This efficient design methodology is tested and considered to be suitable for almost all types of complex FPGA system designs and verifications.

More information

Item ID: 20903
DC Identifier: http://oa.upm.es/20903/
OAI Identifier: oai:oa.upm.es:20903
Official URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6212666
Deposited by: Memoria Investigacion
Deposited on: 19 Nov 2013 16:25
Last Modified: 22 Sep 2014 11:21
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