Hardware-Based Particle Filter with Evolutionary Resampling Stage

Rodríguez Medina, Alfonso (2014). Hardware-Based Particle Filter with Evolutionary Resampling Stage. Tesis (Master), E.T.S.I. Industriales (UPM).

Descripción

Título: Hardware-Based Particle Filter with Evolutionary Resampling Stage
Autor/es:
  • Rodríguez Medina, Alfonso
Director/es:
  • Moreno González, Felix
Tipo de Documento: Tesis (Master)
Título del máster: Electrónica Industrial
Fecha: Marzo 2014
Materias:
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Electrónica, Automática e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - No comercial

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Resumen

Autonomous systems require, in most of the cases, reasoning and decision-making capabilities. Moreover, the decision process has to occur in real time. Real-time computing means that every situation or event has to have an answer before a temporal deadline. In complex applications, these deadlines are usually in the order of milliseconds or even microseconds if the application is very demanding. In order to comply with these timing requirements, computing tasks have to be performed as fast as possible. The problem arises when computations are no longer simple, but very time-consuming operations. A good example can be found in autonomous navigation systems with visual-tracking submodules where Kalman filtering is the most extended solution. However, in recent years, some interesting new approaches have been developed. Particle filtering, given its more general problem-solving features, has reached an important position in the field. The aim of this thesis is to design, implement and validate a hardware platform that constitutes itself an embedded intelligent system. The proposed system would combine particle filtering and evolutionary computation algorithms to generate intelligent behavior. Traditional approaches to particle filtering or evolutionary computation have been developed in software platforms, including parallel capabilities to some extent. In this work, an additional goal is fully exploiting hardware implementation advantages. By using the computational resources available in a FPGA device, better performance results in terms of computation time are expected. These hardware resources will be in charge of extensive repetitive computations. With this hardware-based implementation, real-time features are also expected.

Más información

ID de Registro: 23487
Identificador DC: http://oa.upm.es/23487/
Identificador OAI: oai:oa.upm.es:23487
Depositado por: Alfonso Rodríguez Medina
Depositado el: 11 Abr 2014 10:24
Ultima Modificación: 21 Feb 2017 16:12
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