Low-power vertical cavity NAND gate

Hurtado Villavieja, Antonio; González Marcos, Ana y Martín Pereda, José Antonio (2005). Low-power vertical cavity NAND gate. En: "Photonic Materials, Devices, and Applications", 09/05/2005, Sevilla, España.


Título: Low-power vertical cavity NAND gate
  • Hurtado Villavieja, Antonio
  • González Marcos, Ana
  • Martín Pereda, José Antonio
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: Photonic Materials, Devices, and Applications
Fechas del Evento: 09/05/2005
Lugar del Evento: Sevilla, España
Título del Libro: Proceedings of SPIE
Fecha: 7 Julio 2005
Volumen: 5840
Palabras Clave Informales: Vertical-Cavity Semiconductor Optical Amplifier (VCSOA), Optical Bistability, Logic Gate, Optical Logic, optical computing
Escuela: E.T.S.I. Telecomunicación (UPM)
Departamento: Tecnología Fotónica [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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The study of the Vertical-Cavity Semiconductor Optical Amplifiers (VCSOAs) for optical signal processing applications is increasing his interest. Due to their particular structure, the VCSOAs present some advantages when compared to their edge-emitting counterparts including low manufacturing costs, high coupling efficiency to optical fibers and the ease to fabricate 2-D arrays of this kind of devices. As a consequence, all-optical logic gates based on VCSOAs may be very promising devices for their use in optical computing and optical switching in communications. Moreover, since all the boolean logic functions can be implemented by combining NAND logic gates, the development of a Vertical-Cavity NAND gate would be of particular interest. In this paper, the characteristics of the dispersive optical bistability appearing on a VCSOA operated in reflection are studied. A progressive increment of the number of layers compounding the top Distributed Bragg Reflector (DBR) of the VCSOA results on a change on the shape of the appearing bistability from an S-shape to a clockwise bistable loop. This resulting clockwise bistability has high on-off contrast ratio and input power requirements one order of magnitude lower than those needed for edge-emitting devices. Based on these results, an all-optical vertical-cavity NAND gate with high on-off contrast ratio and an input power for operation of only 10|i\V will be reported in this paper.

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ID de Registro: 26855
Identificador DC: http://oa.upm.es/26855/
Identificador OAI: oai:oa.upm.es:26855
URL Oficial: http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=865964
Depositado por: Biblioteca ETSI Telecomunicación
Depositado el: 02 Jun 2014 05:39
Ultima Modificación: 22 Sep 2014 11:43
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