A novel FPGA-based evolvable hardware system based on multiple processing arrays

Gallego Galán, Ángel and Mora de Sambricio, Javier and Otero Marnotes, Andres and Salvador Perea, Rubén and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). A novel FPGA-based evolvable hardware system based on multiple processing arrays. In: "2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW)", 20/05/2013 - 21/05/2013, Cambridge, Massachusetts, EE.UU. pp. 182-191. https://doi.org/10.1109/IPDPSW.2013.56.

Description

Title: A novel FPGA-based evolvable hardware system based on multiple processing arrays
Author/s:
  • Gallego Galán, Ángel
  • Mora de Sambricio, Javier
  • Otero Marnotes, Andres
  • Salvador Perea, Rubén
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: 2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW)
Event Dates: 20/05/2013 - 21/05/2013
Event Location: Cambridge, Massachusetts, EE.UU
Title of Book: A novel FPGA-based evolvable hardware system based on multiple processing arrays
Date: May 2013
Subjects:
Freetext Keywords: Reconfigurability, adaptability; scalability; evolvable systems, evolvable hardware, fault tolerance, self- healing
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Otro
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

More information

Item ID: 29712
DC Identifier: http://oa.upm.es/29712/
OAI Identifier: oai:oa.upm.es:29712
DOI: 10.1109/IPDPSW.2013.56
Deposited by: Memoria Investigacion
Deposited on: 25 Apr 2015 12:17
Last Modified: 25 May 2015 14:33
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