A novel FPGA-based evolvable hardware system based on multiple processing arrays

Gallego Galán, Ángel; Mora de Sambricio, Javier; Otero Marnotes, Andres; Salvador Perea, Rubén; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2013). A novel FPGA-based evolvable hardware system based on multiple processing arrays. En: "2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW)", 20/05/2013 - 21/05/2013, Cambridge, Massachusetts, EE.UU. pp. 182-191. https://doi.org/10.1109/IPDPSW.2013.56.

Descripción

Título: A novel FPGA-based evolvable hardware system based on multiple processing arrays
Autor/es:
  • Gallego Galán, Ángel
  • Mora de Sambricio, Javier
  • Otero Marnotes, Andres
  • Salvador Perea, Rubén
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW)
Fechas del Evento: 20/05/2013 - 21/05/2013
Lugar del Evento: Cambridge, Massachusetts, EE.UU
Título del Libro: A novel FPGA-based evolvable hardware system based on multiple processing arrays
Fecha: Mayo 2013
Materias:
Palabras Clave Informales: Reconfigurability, adaptability; scalability; evolvable systems, evolvable hardware, fault tolerance, self- healing
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Otro
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

Más información

ID de Registro: 29712
Identificador DC: http://oa.upm.es/29712/
Identificador OAI: oai:oa.upm.es:29712
Identificador DOI: 10.1109/IPDPSW.2013.56
Depositado por: Memoria Investigacion
Depositado el: 25 Abr 2015 12:17
Ultima Modificación: 25 May 2015 14:33
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