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Royer del Barrio, Pablo and López Vallejo, Marisa (2013). Modeling sub-threshold slope and DIBL mismatch of sub-22nm FinFet. In: "8th Conference on Design of Circuits and Integrated Systems (DCIS 2013)", 27/11/2013 - 29/11/2013, San Sebastián, Spain.
Title: | Modeling sub-threshold slope and DIBL mismatch of sub-22nm FinFet |
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Author/s: |
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Item Type: | Presentation at Congress or Conference (Speech) |
Event Title: | 8th Conference on Design of Circuits and Integrated Systems (DCIS 2013) |
Event Dates: | 27/11/2013 - 29/11/2013 |
Event Location: | San Sebastián, Spain |
Title of Book: | 8th Conference on Design of Circuits and Integrated Systems (DCIS 2013) |
Date: | 2013 |
Subjects: | |
Faculty: | E.T.S.I. Telecomunicación (UPM) |
Department: | Ingeniería Electrónica |
Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
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A great challenge for future information technologies is building reliable systems on top of unreliable components. Parameters of modern and future technology devices are affected by severe levels of process variability and devices will degrade and even fail during the normal lifeDme of the chip due to aging mechanisms. These extreme levels of variability are caused by the high device miniaturizaDon and the random placement of individual atoms. Variability is considered a "red brick" by the InternaDonal Technology Roadmap for Semiconductors. The session is devoted to this topic presenDng research experiences from the Spanish Network on Variability called VARIABLES. In this session a talk entlited "Modeling sub-threshold slope and DIBL mismatch of sub-22nm FinFet" was presented.
Item ID: | 30582 |
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DC Identifier: | http://oa.upm.es/30582/ |
OAI Identifier: | oai:oa.upm.es:30582 |
Deposited by: | Memoria Investigacion |
Deposited on: | 17 Sep 2014 19:04 |
Last Modified: | 22 Apr 2016 00:50 |