Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level

Machado Sánchez, Felipe and Riesgo Alcaide, Teresa and Torroja Fungairiño, Yago (2009). Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. In: "18th International Workshop on Power and Timing Modeling, Optimization and Simulation", 10/09/2008-12/09/2008, Lisboa (Portugal). ISBN 978-3-540-95947-2. pp..

Description

Title: Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level
Author/s:
  • Machado Sánchez, Felipe
  • Riesgo Alcaide, Teresa
  • Torroja Fungairiño, Yago
Item Type: Presentation at Congress or Conference (Article)
Event Title: 18th International Workshop on Power and Timing Modeling, Optimization and Simulation
Event Dates: 10/09/2008-12/09/2008
Event Location: Lisboa (Portugal)
Title of Book: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Date: 2009
ISBN: 978-3-540-95947-2
Volume: XIII
Subjects:
Freetext Keywords: Switching activity, CAD, RTL, BDD, activity estimation, digital circuit design, VHDL, circuit partition, power estimation.
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits; therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits; whilst error seems to decrease with the circuit size.

More information

Item ID: 3354
DC Identifier: http://oa.upm.es/3354/
OAI Identifier: oai:oa.upm.es:3354
Official URL: http://www.springer.com/computer/hardware/book/978-3-540-95947-2
Deposited by: Memoria Investigacion
Deposited on: 17 Jun 2010 09:14
Last Modified: 20 Apr 2016 12:54
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