Mimo Systems Low complexity SVD Implementation Analysis

Benavente Peces, César and Arriero Encinas, Luis and Osés del Campo, David and Ortega González, Francisco Javier and Pardo Martin, José Manuel (2008). Mimo Systems Low complexity SVD Implementation Analysis. In: "XXIII Simposium Nacional de la Unión Científica Internacional de Radio.URSI 2008", 22/09/2008-24/09/2008, Madrid, España. ISBN 978-84-612-6290-8.

Description

Title: Mimo Systems Low complexity SVD Implementation Analysis
Author/s:
  • Benavente Peces, César
  • Arriero Encinas, Luis
  • Osés del Campo, David
  • Ortega González, Francisco Javier
  • Pardo Martin, José Manuel
Item Type: Presentation at Congress or Conference (Article)
Event Title: XXIII Simposium Nacional de la Unión Científica Internacional de Radio.URSI 2008
Event Dates: 22/09/2008-24/09/2008
Event Location: Madrid, España
Title of Book: Actas del XXIII Simposium Nacional de la Unión Científica Internacional de Radio
Date: 22 September 2008
ISBN: 978-84-612-6290-8
Subjects:
Faculty: E.U.I.T. Telecomunicación (UPM)
Department: Ingeniería de Circuitos y Sistemas [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

This paper analyses the implementation of the singular value decomposition (SVD) using approximation to the exact computation for MIMO systems in the case of modulation-mode and power assignment set-up. The study developed in the paper focuses on the use of low complexity algorithm with low computational load oriented to the use of devices with limited resources as FPGA, highlighting some of the advantages and drawbacks against more sophisticated devices. The implementation of the SVD is analyzed through the algorithms that efficiently perform the required computations, seeking for computationally efficient solutions that provide parallelism and low complexity. The CORDIC algorithm seems to be a good candidate for this task since it can efficiently compute the singular value decomposition. It is shown that this algorithm provides an efficient tool for SVD computation with appropriate accuracy and the computational complexity obtained and the required resources make it feasible to be implemented on an FPGA device. System performance degradation is analyzed compared with conventional and exact method for SVD obtaining some key conclusions.

More information

Item ID: 3374
DC Identifier: http://oa.upm.es/3374/
OAI Identifier: oai:oa.upm.es:3374
Official URL: http://gass.ucm.es/URSI2008/simposium/inicio.html
Deposited by: Memoria Investigacion
Deposited on: 28 Jun 2010 10:17
Last Modified: 20 Apr 2016 12:55
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