Wireless Sensor Networks Node with Remote HW/SW Reconfiguration Capabilities

Portilla Berrueco, Jorge and Esteves Krasteva, Yana and Carnicer, Jose María and Riesgo Alcaide, Teresa (2009). Wireless Sensor Networks Node with Remote HW/SW Reconfiguration Capabilities. In: "23rd Conference on Design of Circuits and Integrated Systems, DCIS 2008", 12/11/2008-14/11/2008, Granoble, Francia. ISBN 978-28-4813-124-5.

Description

Title: Wireless Sensor Networks Node with Remote HW/SW Reconfiguration Capabilities
Author/s:
  • Portilla Berrueco, Jorge
  • Esteves Krasteva, Yana
  • Carnicer, Jose María
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: 23rd Conference on Design of Circuits and Integrated Systems, DCIS 2008
Event Dates: 12/11/2008-14/11/2008
Event Location: Granoble, Francia
Title of Book: Proceedings of the 23rd Conference on Design of Circuits and Integrated Systems, DCIS 2008
Date: 2009
ISBN: 978-28-4813-124-5
Subjects:
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

The inclusion of reconfigurable HW in nodes for Wireless Sensor Networks (WSNs) is not a common issue in the framework of the design of state of the art HW platforms for WSNs, mainly due to its high power consumption. But, on the other hand, reconfigurable logic as FPGAs can contribute to improve the system performance by providing not only HW acceleration as it has already been demonstrated by several research groups, but also the possibility of node HW updates after WSN deployment. This paper presents an entire working flow to generate, remotely configure and reconfigure the HW and SW in a reconfigurable node platform for WSNs. The presented reconfiguration working flow targets the custom HW platform designed at CEI (Centro de Electronica Industrial), where the processing is carried out by both a microcontroller and a partially reconfigurable Xilinx FPGA. The presented reconfiguration process is based on the JTAG protocol and thus permits to port the system to new, less power consuming FPGAs that are appearing in the market to solve problems related to energy lifetime

More information

Item ID: 3435
DC Identifier: http://oa.upm.es/3435/
OAI Identifier: oai:oa.upm.es:3435
Official URL: http://www.dcis.org/
Deposited by: Memoria Investigacion
Deposited on: 09 Mar 2011 10:06
Last Modified: 20 Apr 2016 12:59
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