Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

Royer del Barrio, Pablo y López Vallejo, Marisa (2014). Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies. "IEEE Transactions on Nanotechnology", v. 13 (n. 6); pp. 1226-1233. ISSN 1536-125X. https://doi.org/10.1109/TNANO.2014.2354073.

Descripción

Título: Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies
Autor/es:
  • Royer del Barrio, Pablo
  • López Vallejo, Marisa
Tipo de Documento: Artículo
Título de Revista/Publicación: IEEE Transactions on Nanotechnology
Fecha: Noviembre 2014
Volumen: 13
Materias:
Palabras Clave Informales: Complementary SRAM, fin-shaped field-effecttransistor (FinFET), mismatch, pass-gate, SiGe stressor, static random access memory (SRAM), tensile stress, variability
Escuela: E.T.S.I. Telecomunicación (UPM)
Departamento: Ingeniería Electrónica
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors.

Más información

ID de Registro: 35985
Identificador DC: http://oa.upm.es/35985/
Identificador OAI: oai:oa.upm.es:35985
Identificador DOI: 10.1109/TNANO.2014.2354073
URL Oficial: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6868984
Depositado por: Memoria Investigacion
Depositado el: 01 Jul 2015 16:46
Ultima Modificación: 01 Jul 2015 16:46
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