Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

Royer del Barrio, Pablo and López Vallejo, Marisa (2014). Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies. "IEEE Transactions on Nanotechnology", v. 13 (n. 6); pp. 1226-1233. ISSN 1536-125X. https://doi.org/10.1109/TNANO.2014.2354073.

Description

Title: Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies
Author/s:
  • Royer del Barrio, Pablo
  • López Vallejo, Marisa
Item Type: Article
Título de Revista/Publicación: IEEE Transactions on Nanotechnology
Date: November 2014
ISSN: 1536-125X
Volume: 13
Subjects:
Freetext Keywords: Complementary SRAM, fin-shaped field-effecttransistor (FinFET), mismatch, pass-gate, SiGe stressor, static random access memory (SRAM), tensile stress, variability
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors.

More information

Item ID: 35985
DC Identifier: http://oa.upm.es/35985/
OAI Identifier: oai:oa.upm.es:35985
DOI: 10.1109/TNANO.2014.2354073
Official URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6868984
Deposited by: Memoria Investigacion
Deposited on: 01 Jul 2015 16:46
Last Modified: 01 Jul 2015 16:46
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