A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems

Valverde Alcalá, Juan and Rodríguez, A. and Camarero, J.J. and Otero, A. and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems. In: "24th International Conference on Field Programmable Logic and Applications", September 1 - 5, 2014, Munich (Germany). pp. 1-4.

Description

Title: A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems
Author/s:
  • Valverde Alcalá, Juan
  • Rodríguez, A.
  • Camarero, J.J.
  • Otero, A.
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: 24th International Conference on Field Programmable Logic and Applications
Event Dates: September 1 - 5, 2014
Event Location: Munich (Germany)
Title of Book: Conference Digest. 24th International Conference on Field Programmable Logic and Applications
Date: 2014
Subjects:
Freetext Keywords: Cyber-Physical Systems, Dynamic and Partial Reconfiguration, FPGAs, Wireless Sensor Networks, Parallel processing, Dependability.
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

Funding Projects

TypeCodeAcronymLeaderTitle
UnspecifiedTE C2011 - 28666 - C04 - 02DREAMSUnspecifiedDynamically Reconfigurable Embedded Platforms for Networked Context-Aware Multimedia Systems

More information

Item ID: 37014
DC Identifier: http://oa.upm.es/37014/
OAI Identifier: oai:oa.upm.es:37014
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6927394&tag=1
Deposited by: Memoria Investigacion
Deposited on: 16 Mar 2016 15:33
Last Modified: 16 Mar 2016 15:33
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