A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems

Valverde Alcalá, Juan; Rodríguez, A.; Camarero, J.J.; Otero, A.; Portilla Berrueco, Jorge; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2014). A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems. En: "24th International Conference on Field Programmable Logic and Applications", September 1 - 5, 2014, Munich (Germany). pp. 1-4.

Descripción

Título: A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems
Autor/es:
  • Valverde Alcalá, Juan
  • Rodríguez, A.
  • Camarero, J.J.
  • Otero, A.
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 24th International Conference on Field Programmable Logic and Applications
Fechas del Evento: September 1 - 5, 2014
Lugar del Evento: Munich (Germany)
Título del Libro: Conference Digest. 24th International Conference on Field Programmable Logic and Applications
Fecha: 2014
Materias:
Palabras Clave Informales: Cyber-Physical Systems, Dynamic and Partial Reconfiguration, FPGAs, Wireless Sensor Networks, Parallel processing, Dependability.
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

Texto completo

[img]
Vista Previa
PDF (Document Portable Format) - Se necesita un visor de ficheros PDF, como GSview, Xpdf o Adobe Acrobat Reader
Descargar (1MB) | Vista Previa

Resumen

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

Proyectos asociados

TipoCódigoAcrónimoResponsableTítulo
Sin especificarTE C2011 - 28666 - C04 - 02DREAMSSin especificarDynamically Reconfigurable Embedded Platforms for Networked Context-Aware Multimedia Systems

Más información

ID de Registro: 37014
Identificador DC: http://oa.upm.es/37014/
Identificador OAI: oai:oa.upm.es:37014
URL Oficial: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6927394&tag=1
Depositado por: Memoria Investigacion
Depositado el: 16 Mar 2016 15:33
Ultima Modificación: 16 Mar 2016 15:33
  • Open Access
  • Open Access
  • Sherpa-Romeo
    Compruebe si la revista anglosajona en la que ha publicado un artículo permite también su publicación en abierto.
  • Dulcinea
    Compruebe si la revista española en la que ha publicado un artículo permite también su publicación en abierto.
  • Recolecta
  • e-ciencia
  • Observatorio I+D+i UPM
  • OpenCourseWare UPM