A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor

Veljković, Filip and Riesgo Alcaide, Teresa and Torre Arnanz, Eduardo de la and Regada, Raúl and Berrojo, Luis (2014). A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. In: "2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 14/07/2014 17/07/2014, Leicester, United Kingdom. pp. 143-150. https://doi.org/10.1109/AHS.2014.6880170.

Description

Title: A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor
Author/s:
  • Veljković, Filip
  • Riesgo Alcaide, Teresa
  • Torre Arnanz, Eduardo de la
  • Regada, Raúl
  • Berrojo, Luis
Item Type: Presentation at Congress or Conference (Article)
Event Title: 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Event Dates: 14/07/2014 17/07/2014
Event Location: Leicester, United Kingdom
Title of Book: 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Date: 2014
Subjects:
Freetext Keywords: Fault tolerance, ICAP, duplex, TMR, voting, scalability, run-time partial reconfiguration, FPGAs, DVB-OBP
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Reliability is one of the key issues in space applications. Although highly flexible and generally less expensive than predominantly used ASICs, SRAM-based FPGAs are very susceptible to radiation effects. Hence, various fault tolerant techniques have to be applied in order to handle faults and protect the design. This paper presents a reconfigurable on-board processor capable of run-time adaptation to harsh environmental conditions and different functional demands. Run-time reconfigurability is achieved applying two different reconfiguration methodologies. We propose a novel self-reconfigurable architecture able to on demand duplicate or triplicate part of the design in order to form DMR and TMR structures. Moreover, we introduce two different approaches for voting the correct output. The first one is a traditional voter that adapts to different DMR/TMR domain positions whereas the second implies comparing the captured flip-flop values directly from the configuration memory read through ICAP. The comparison is done periodically by an embedded processor thus completely excluding the voting mechanism in hardware. The proposed run-time reconfiguration methodology provides savings in terms of device utilization, reconfiguration time, power consumption and significant reductions in the amount of rad-hard memory used by partial configurations.

More information

Item ID: 37138
DC Identifier: http://oa.upm.es/37138/
OAI Identifier: oai:oa.upm.es:37138
DOI: 10.1109/AHS.2014.6880170
Official URL: http://ieeexplore.ieee.org/document/6880170/
Deposited by: Memoria Investigacion
Deposited on: 01 Apr 2017 11:38
Last Modified: 01 Apr 2017 12:05
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