A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor

Veljković, Filip; Riesgo Alcaide, Teresa; Torre Arnanz, Eduardo de la; Regada, Raúl y Berrojo, Luis (2014). A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. En: "2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 14/07/2014 17/07/2014, Leicester, United Kingdom. pp. 143-150. https://doi.org/10.1109/AHS.2014.6880170.

Descripción

Título: A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor
Autor/es:
  • Veljković, Filip
  • Riesgo Alcaide, Teresa
  • Torre Arnanz, Eduardo de la
  • Regada, Raúl
  • Berrojo, Luis
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Fechas del Evento: 14/07/2014 17/07/2014
Lugar del Evento: Leicester, United Kingdom
Título del Libro: 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Fecha: 2014
Materias:
Palabras Clave Informales: Fault tolerance, ICAP, duplex, TMR, voting, scalability, run-time partial reconfiguration, FPGAs, DVB-OBP
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Reliability is one of the key issues in space applications. Although highly flexible and generally less expensive than predominantly used ASICs, SRAM-based FPGAs are very susceptible to radiation effects. Hence, various fault tolerant techniques have to be applied in order to handle faults and protect the design. This paper presents a reconfigurable on-board processor capable of run-time adaptation to harsh environmental conditions and different functional demands. Run-time reconfigurability is achieved applying two different reconfiguration methodologies. We propose a novel self-reconfigurable architecture able to on demand duplicate or triplicate part of the design in order to form DMR and TMR structures. Moreover, we introduce two different approaches for voting the correct output. The first one is a traditional voter that adapts to different DMR/TMR domain positions whereas the second implies comparing the captured flip-flop values directly from the configuration memory read through ICAP. The comparison is done periodically by an embedded processor thus completely excluding the voting mechanism in hardware. The proposed run-time reconfiguration methodology provides savings in terms of device utilization, reconfiguration time, power consumption and significant reductions in the amount of rad-hard memory used by partial configurations.

Más información

ID de Registro: 37138
Identificador DC: http://oa.upm.es/37138/
Identificador OAI: oai:oa.upm.es:37138
Identificador DOI: 10.1109/AHS.2014.6880170
URL Oficial: http://ieeexplore.ieee.org/document/6880170/
Depositado por: Memoria Investigacion
Depositado el: 01 Abr 2017 11:38
Ultima Modificación: 01 Abr 2017 12:05
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