Analysis of design alternatives on using dynamic and partial reconfiguration in a space application

Veljković, Filip and Riesgo Alcaide, Teresa and Berrojo, Luis and Regada, Raúl and Álvaro Castellanos, Ángel de and Torre Arnanz, Eduardo de la (2014). Analysis of design alternatives on using dynamic and partial reconfiguration in a space application. In: "Data Systems in Aerospace (DASIA 2014)", 03/06/2014 - 05/06/2014, Warsaw, Poland. pp. 1-7.

Description

Title: Analysis of design alternatives on using dynamic and partial reconfiguration in a space application
Author/s:
  • Veljković, Filip
  • Riesgo Alcaide, Teresa
  • Berrojo, Luis
  • Regada, Raúl
  • Álvaro Castellanos, Ángel de
  • Torre Arnanz, Eduardo de la
Item Type: Presentation at Congress or Conference (Article)
Event Title: Data Systems in Aerospace (DASIA 2014)
Event Dates: 03/06/2014 - 05/06/2014
Event Location: Warsaw, Poland
Title of Book: Data Systems in Aerospace (DASIA 2014)
Date: 2014
Volume: 725
Subjects:
Freetext Keywords: SRAM-based FPGAs; scalable dynamic and partial reconfiguration; scalability; on-board processor; space application
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

Full text

[img]
Preview
PDF - Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader
Download (679kB) | Preview

Abstract

Some of the biggest concerns in space systems are power consumption and reliability due to the limited power generated by the system's energy harvesters and the fact that once deployed, it is almost impossible to perform maintenance or repairs. Another consideration is that during deployment, the high exposure to electromagnetic radiation can cause single event damage effects including SEUs, SEFIs, SETs and others. In order to mitigate these problems inherent to the space environment, a system with dynamic and partial reconfiguration capabilities is proposed. This approach provide s the flexibility to reconfigure parts of the FPGA while still in operation, thus making the system more flexible, fault tolerant and less power-consuming. In this paper, several partial reconfiguration approaches are proposed and compared in terms of device occupation, power consumption, reconfiguration speed and size of memory footprints.

More information

Item ID: 37139
DC Identifier: http://oa.upm.es/37139/
OAI Identifier: oai:oa.upm.es:37139
Deposited by: Memoria Investigacion
Deposited on: 01 Apr 2017 11:47
Last Modified: 01 Apr 2017 11:47
  • Logo InvestigaM (UPM)
  • Logo GEOUP4
  • Logo Open Access
  • Open Access
  • Logo Sherpa/Romeo
    Check whether the anglo-saxon journal in which you have published an article allows you to also publish it under open access.
  • Logo Dulcinea
    Check whether the spanish journal in which you have published an article allows you to also publish it under open access.
  • Logo de Recolecta
  • Logo del Observatorio I+D+i UPM
  • Logo de OpenCourseWare UPM