Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

Rodríguez Medina, Alfonso; Valverde Alcalá, Juan y Torre Arnanz, Eduardo de la (2015). Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. En: "International Conference on ReConFigurable Computing and FPGAs (ReConFig 2015)", 07/12/2015 - 9/12/2015, Bremen, Germany. pp. 1-8. https://doi.org/10.1109/ReConFig.2015.7393297.

Descripción

Título: Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs
Autor/es:
  • Rodríguez Medina, Alfonso
  • Valverde Alcalá, Juan
  • Torre Arnanz, Eduardo de la
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: International Conference on ReConFigurable Computing and FPGAs (ReConFig 2015)
Fechas del Evento: 07/12/2015 - 9/12/2015
Lugar del Evento: Bremen, Germany
Título del Libro: International Conference on ReConFigurable Computing and FPGAs (ReConFig 2015)
Fecha: 2015
Materias:
Palabras Clave Informales: —Multithreading, Hardware Accelerators, Dynamic and Partial Reconfiguration, Fault Tolerance, OpenCL, FPGAs
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support. In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a memory model based on shared memory between host and compute device, which removes the overhead imposed by data transferences at global memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global memory through optimized DMA links. These local memories provide unified access, i.e. a continuous memory map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.

Proyectos asociados

TipoCódigoAcrónimoResponsableTítulo
Gobierno de EspañaTEC2014-58036-C4-2-RREBECCAMinisterio de Economía y CompetitividadSin especificar

Más información

ID de Registro: 42584
Identificador DC: http://oa.upm.es/42584/
Identificador OAI: oai:oa.upm.es:42584
Identificador DOI: 10.1109/ReConFig.2015.7393297
URL Oficial: http://ieeexplore.ieee.org/document/7393297/
Depositado por: Memoria Investigacion
Depositado el: 22 Abr 2017 07:48
Ultima Modificación: 22 Abr 2017 07:48
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