Execution modeling in self-aware FPGA-based architectures for efficient resource management

Rodríguez Medina, Alfonso; Valverde Alcalá, Juan; Castañares Franco, César; Portilla Berrueco, Jorge; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2015). Execution modeling in self-aware FPGA-based architectures for efficient resource management. En: "10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)", 29/06/2015 - 01/07/2015, Bremen, Germany. pp. 1-8. https://doi.org/10.1109/ReCoSoC.2015.7238086.

Descripción

Título: Execution modeling in self-aware FPGA-based architectures for efficient resource management
Autor/es:
  • Rodríguez Medina, Alfonso
  • Valverde Alcalá, Juan
  • Castañares Franco, César
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Fechas del Evento: 29/06/2015 - 01/07/2015
Lugar del Evento: Bremen, Germany
Título del Libro: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Fecha: 2015
Materias:
Palabras Clave Informales: Self-awareness, dynamic and partial reconfiguration, dynamic resource management, FPGAs
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

SRAM-based FPGAs have significantly improved their performance and size with the use of newer and ultra-deep-submicron technologies, even though power consumption, together with a time-consuming initial configuration process, are still major concerns when targeting energy-efficient solutions. System self-awareness enables the use of strategies to enhance system performance and power optimization taking into account run-time metrics. This is of particular importance when dealing with reconfigurable systems that may make use of such information for efficient resource management, such as in the case of the ARTICo3 architecture, which fosters dynamic execution of kernels formed by multiple blocks of threads allocated in a variable number of hardware accelerators, combined with module redundancy for fault tolerance and other dependability enhancements, e.g. side-channel-attack protection. In this paper, a model for efficient dynamic resource management focused on both power consumption and execution times in the ARTICo3 architecture is proposed. The approach enables the characterization of kernel execution by using the model, providing additional decision criteria based on energy efficiency, so that resource allocation and scheduling policies may adapt to changing conditions. Two different platforms have been used to validate the proposal and show the generalization of the model: a high-performance wireless sensor node based on a Spartan-6 and a standard off-the-shelf development board based on a Kintex-7.

Proyectos asociados

TipoCódigoAcrónimoResponsableTítulo
Gobierno de EspañaTEC2014-58036-C4-2-RREBECCAMinisterio de Economía y CompetitividadSin especificar

Más información

ID de Registro: 42588
Identificador DC: http://oa.upm.es/42588/
Identificador OAI: oai:oa.upm.es:42588
Identificador DOI: 10.1109/ReCoSoC.2015.7238086
URL Oficial: http://ieeexplore.ieee.org/document/7238086/
Depositado por: Memoria Investigacion
Depositado el: 22 Abr 2017 08:11
Ultima Modificación: 22 Abr 2017 08:11
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