Execution modeling in self-aware FPGA-based architectures for efficient resource management

Rodríguez Medina, Alfonso and Valverde Alcalá, Juan and Castañares Franco, César and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2015). Execution modeling in self-aware FPGA-based architectures for efficient resource management. In: "10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)", 29/06/2015 - 01/07/2015, Bremen, Germany. pp. 1-8. https://doi.org/10.1109/ReCoSoC.2015.7238086.

Description

Title: Execution modeling in self-aware FPGA-based architectures for efficient resource management
Author/s:
  • Rodríguez Medina, Alfonso
  • Valverde Alcalá, Juan
  • Castañares Franco, César
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Event Dates: 29/06/2015 - 01/07/2015
Event Location: Bremen, Germany
Title of Book: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Date: 2015
Subjects:
Freetext Keywords: Self-awareness, dynamic and partial reconfiguration, dynamic resource management, FPGAs
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

SRAM-based FPGAs have significantly improved their performance and size with the use of newer and ultra-deep-submicron technologies, even though power consumption, together with a time-consuming initial configuration process, are still major concerns when targeting energy-efficient solutions. System self-awareness enables the use of strategies to enhance system performance and power optimization taking into account run-time metrics. This is of particular importance when dealing with reconfigurable systems that may make use of such information for efficient resource management, such as in the case of the ARTICo3 architecture, which fosters dynamic execution of kernels formed by multiple blocks of threads allocated in a variable number of hardware accelerators, combined with module redundancy for fault tolerance and other dependability enhancements, e.g. side-channel-attack protection. In this paper, a model for efficient dynamic resource management focused on both power consumption and execution times in the ARTICo3 architecture is proposed. The approach enables the characterization of kernel execution by using the model, providing additional decision criteria based on energy efficiency, so that resource allocation and scheduling policies may adapt to changing conditions. Two different platforms have been used to validate the proposal and show the generalization of the model: a high-performance wireless sensor node based on a Spartan-6 and a standard off-the-shelf development board based on a Kintex-7.

Funding Projects

TypeCodeAcronymLeaderTitle
Government of SpainTEC2014-58036-C4-2-RREBECCAMinisterio de Economía y CompetitividadUnspecified

More information

Item ID: 42588
DC Identifier: http://oa.upm.es/42588/
OAI Identifier: oai:oa.upm.es:42588
DOI: 10.1109/ReCoSoC.2015.7238086
Official URL: http://ieeexplore.ieee.org/document/7238086/
Deposited by: Memoria Investigacion
Deposited on: 22 Apr 2017 08:11
Last Modified: 22 Apr 2017 08:11
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