Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

Mora de Sambricio, Javier; Otero Marnotes, Andres; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2015). Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. En: "10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)", 29/06/2015 - 01/07/2015, Bremen, Germany. pp. 1-7. https://doi.org/10.1109/ReCoSoC.2015.7238087.

Descripción

Título: Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs
Autor/es:
  • Mora de Sambricio, Javier
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Fechas del Evento: 29/06/2015 - 01/07/2015
Lugar del Evento: Bremen, Germany
Título del Libro: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Fecha: 2015
Materias:
Palabras Clave Informales: FPGA, evolvable hardware, systolic array, partial reconfiguration, LUT
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Evolvable hardware may be considered as the result of a design methodology that employs an evolutionary algorithm to find an optimal solution to a given problem in the form of a digital circuit. Evolutionary algorithms typically require testing thousands of candidate solutions, taking long time to complete. It would be desirable to reduce this time to a few seconds for applications that require a fast adaptation to a problem. Also, it is important to consider architectures that may operate at high clock speeds in order to reach very speed-demanding situations. This paper presents an implementation on an FPGA of an evolvable hardware image filter based on a systolic array architecture that uses dynamic partial reconfiguration in order to change between different candidate solutions. The neighbor to neighbor connections of the array offer improved performance versus other approaches, like Cartesian Genetic Programming derived circuits. Time savings due to faster evaluation compensate the slower reconfiguration time compared with virtual reconfiguration approaches, but, at any rate, reconfiguration time has been improved also by reducing the elements to reconfigure to just the LUT contents of the configurable blocks. The techniques presented in this paper lead to circuits that may operate at up to 500 MHz (in a Virtex-5), filtering 500 megapixels per second, the processing element size of the array is reduced to 2 CLBs, and over 80000 evaluations per second in a multiplearray structure in an FPGA permit to obtain good quality filters in around 3 seconds of evolution time.

Proyectos asociados

TipoCódigoAcrónimoResponsableTítulo
Comunidad de MadridTEC2014-58036-C4-2-RREBECCAMinisterio de Economía y CompetitividadSin especificar

Más información

ID de Registro: 42597
Identificador DC: http://oa.upm.es/42597/
Identificador OAI: oai:oa.upm.es:42597
Identificador DOI: 10.1109/ReCoSoC.2015.7238087
URL Oficial: http://ieeexplore.ieee.org/document/7238087/
Depositado por: Memoria Investigacion
Depositado el: 25 Abr 2017 15:20
Ultima Modificación: 25 Abr 2017 15:20
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