Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

Mora de Sambricio, Javier and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2015). Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. In: "10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)", 29/06/2015 - 01/07/2015, Bremen, Germany. pp. 1-7. https://doi.org/10.1109/ReCoSoC.2015.7238087.

Description

Title: Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs
Author/s:
  • Mora de Sambricio, Javier
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Event Dates: 29/06/2015 - 01/07/2015
Event Location: Bremen, Germany
Title of Book: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
Date: 2015
Subjects:
Freetext Keywords: FPGA, evolvable hardware, systolic array, partial reconfiguration, LUT
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Evolvable hardware may be considered as the result of a design methodology that employs an evolutionary algorithm to find an optimal solution to a given problem in the form of a digital circuit. Evolutionary algorithms typically require testing thousands of candidate solutions, taking long time to complete. It would be desirable to reduce this time to a few seconds for applications that require a fast adaptation to a problem. Also, it is important to consider architectures that may operate at high clock speeds in order to reach very speed-demanding situations. This paper presents an implementation on an FPGA of an evolvable hardware image filter based on a systolic array architecture that uses dynamic partial reconfiguration in order to change between different candidate solutions. The neighbor to neighbor connections of the array offer improved performance versus other approaches, like Cartesian Genetic Programming derived circuits. Time savings due to faster evaluation compensate the slower reconfiguration time compared with virtual reconfiguration approaches, but, at any rate, reconfiguration time has been improved also by reducing the elements to reconfigure to just the LUT contents of the configurable blocks. The techniques presented in this paper lead to circuits that may operate at up to 500 MHz (in a Virtex-5), filtering 500 megapixels per second, the processing element size of the array is reduced to 2 CLBs, and over 80000 evaluations per second in a multiplearray structure in an FPGA permit to obtain good quality filters in around 3 seconds of evolution time.

Funding Projects

TypeCodeAcronymLeaderTitle
Madrid Regional GovernmentTEC2014-58036-C4-2-RREBECCAMinisterio de Economía y CompetitividadUnspecified

More information

Item ID: 42597
DC Identifier: http://oa.upm.es/42597/
OAI Identifier: oai:oa.upm.es:42597
DOI: 10.1109/ReCoSoC.2015.7238087
Official URL: http://ieeexplore.ieee.org/document/7238087/
Deposited by: Memoria Investigacion
Deposited on: 25 Apr 2017 15:20
Last Modified: 25 Apr 2017 15:20
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