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Pipeline-Based Power Reduction in FPGA Applications
Citation
Sacristán, Miguel Angel and Rodellar Biarge, M. Victoria and Díaz Lavadores, Antonio (2008). Pipeline-Based Power Reduction in FPGA Applications. In: "SPL2008 - IV Southern Conference on Programmable Logic", 26/03/2008-28/03/2008, Patagonia, Argentina. ISBN 978-84-612-2376-3.
Description
| Title: | Pipeline-Based Power Reduction in FPGA Applications |
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| Author/s: |
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| Item Type: | Presentation at Congress or Conference (Article) |
| Event Title: | SPL2008 - IV Southern Conference on Programmable Logic |
| Event Dates: | 26/03/2008-28/03/2008 |
| Event Location: | Patagonia, Argentina |
| Title of Book: | Proceedings of the IV Southern Conference on Programmable Logic, SPL2008 |
| Date: | 2008 |
| ISBN: | 978-84-612-2376-3 |
| Subjects: | |
| Faculty: | Facultad de Informática (UPM) |
| Department: | Arquitectura y Tecnología de Sistemas Informáticos |
| Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
Abstract
This paper shows how temporal parallelism has an important role in the power dissipation reduction in the FPGA field. Glitches propagation is blocked by the flip-flops or registers in the pipeline. Several multiplication structures are implemented over modern FPGAs, StratixII and Virtex4, comparing their results with and without pipeline and hardware duplication.
More information
| Item ID: | 4678 |
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| DC Identifier: | http://oa.upm.es/4678/ |
| OAI Identifier: | oai:oa.upm.es:4678 |
| Official URL: | http://www.splconf.org/spl08/ |
| Deposited by: | Memoria Investigacion |
| Deposited on: | 25 Oct 2010 07:59 |
| Last Modified: | 20 Apr 2016 13:48 |
