Power Estimation Technique for DSP Architectures.

Durrani, Yaseer A. and Riesgo Alcaide, Teresa (2009). Power Estimation Technique for DSP Architectures.. "Digital Signal Processing.", v. 19 (n. 2); pp. 213-219. ISSN 1051-2004.


Title: Power Estimation Technique for DSP Architectures.
  • Durrani, Yaseer A.
  • Riesgo Alcaide, Teresa
Item Type: Article
Título de Revista/Publicación: Digital Signal Processing.
Date: March 2009
Volume: 19
Freetext Keywords: Macromodel, DSP architecture, Digital filter, Power estimation, Intellectual property, Monte Carlo simulation
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Official URL: http://www.elsevier.com/locate/dsp


The main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modeling technique for digital signal processing (DSP) architectures in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate power dissipation of the system just by using the statistics of the macro-block’s primary in puts. In experiments with the DSP system, the average error is 26%.

More information

Item ID: 5087
DC Identifier: http://oa.upm.es/5087/
OAI Identifier: oai:oa.upm.es:5087
Deposited by: Memoria Investigacion
Deposited on: 24 Nov 2010 11:53
Last Modified: 20 Apr 2016 14:02
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