Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs

Liu, Yidi and Villaverde San José, Mónica and Moreno González, Félix Antonio and Carrión Schafer, Benjamín (2017). Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs. In: "12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)", 12-14 July 2017, Madrid (Spain). pp. 1-5. https://doi.org/10.1109/ReCoSoC.2017.8016158.

Description

Title: Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs
Author/s:
  • Liu, Yidi
  • Villaverde San José, Mónica
  • Moreno González, Félix Antonio
  • Carrión Schafer, Benjamín
Item Type: Presentation at Congress or Conference (Article)
Event Title: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)
Event Dates: 12-14 July 2017
Event Location: Madrid (Spain)
Title of Book: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017) : Proceedings
Date: 2017
Subjects:
Freetext Keywords: Multi-processor system-on-chips; High-Level Synthesis; Behavioral IP; System Exploration
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

This work presents a method to characterize and optimize hardware accelerators (HWaccs) given as Behavioral IPs (BIPs) mapped as loosely coupled HWaccs in heterogenous MPSoCs. The proposed HWacc exploration flow is composed of two main stages. The first stage characterizes each BIPs individually by performing a High-Level Synthesis (HLS) Design Space Exploration (DSE) on each of the BIPs to obtain a trade-off curve of Pareto-optimal designs. It then continues by exploring the system-level design space using these Pareto-optimal designs and finding configurations with unique area vs. performance trade-offs. Our proposed system-level explorer makes use of cycle-accurate simulation models to explore the search space fast and accurately. Experimental results show that our proposed method works well for MPSoCs of different sizes ranging from systems with 1 to 4 masters and with 3 to 7 HWaccs.

More information

Item ID: 51100
DC Identifier: http://oa.upm.es/51100/
OAI Identifier: oai:oa.upm.es:51100
DOI: 10.1109/ReCoSoC.2017.8016158
Official URL: https://ieeexplore.ieee.org/document/8016158
Deposited by: Memoria Investigacion
Deposited on: 11 Oct 2018 15:29
Last Modified: 11 Oct 2018 15:29
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