Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs

Liu, Yidi; Villaverde San José, Mónica; Moreno González, Félix Antonio y Carrión Schafer, Benjamín (2017). Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs. En: "12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)", 12-14 July 2017, Madrid (Spain). pp. 1-5. https://doi.org/10.1109/ReCoSoC.2017.8016158.

Descripción

Título: Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs
Autor/es:
  • Liu, Yidi
  • Villaverde San José, Mónica
  • Moreno González, Félix Antonio
  • Carrión Schafer, Benjamín
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017)
Fechas del Evento: 12-14 July 2017
Lugar del Evento: Madrid (Spain)
Título del Libro: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017) : Proceedings
Fecha: 2017
Materias:
Palabras Clave Informales: Multi-processor system-on-chips; High-Level Synthesis; Behavioral IP; System Exploration
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

This work presents a method to characterize and optimize hardware accelerators (HWaccs) given as Behavioral IPs (BIPs) mapped as loosely coupled HWaccs in heterogenous MPSoCs. The proposed HWacc exploration flow is composed of two main stages. The first stage characterizes each BIPs individually by performing a High-Level Synthesis (HLS) Design Space Exploration (DSE) on each of the BIPs to obtain a trade-off curve of Pareto-optimal designs. It then continues by exploring the system-level design space using these Pareto-optimal designs and finding configurations with unique area vs. performance trade-offs. Our proposed system-level explorer makes use of cycle-accurate simulation models to explore the search space fast and accurately. Experimental results show that our proposed method works well for MPSoCs of different sizes ranging from systems with 1 to 4 masters and with 3 to 7 HWaccs.

Más información

ID de Registro: 51100
Identificador DC: http://oa.upm.es/51100/
Identificador OAI: oai:oa.upm.es:51100
Identificador DOI: 10.1109/ReCoSoC.2017.8016158
URL Oficial: https://ieeexplore.ieee.org/document/8016158
Depositado por: Memoria Investigacion
Depositado el: 11 Oct 2018 15:29
Ultima Modificación: 11 Oct 2018 15:29
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