Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC

Suriano, Leonardo and Rodriguez, Alfonso and Desnos, Karol and Pelcat, Maxime and Torre Arnanz, Eduardo de la (2017). Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC. In: "2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)", 12-14 Julio 2017, Madrid, Spain. https://doi.org/10.1109/ReCoSoC.2017.8016151.

Description

Title: Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC
Author/s:
  • Suriano, Leonardo
  • Rodriguez, Alfonso
  • Desnos, Karol
  • Pelcat, Maxime
  • Torre Arnanz, Eduardo de la
Item Type: Presentation at Congress or Conference (Article)
Event Title: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Event Dates: 12-14 Julio 2017
Event Location: Madrid, Spain
Title of Book: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Date: 14 July 2017
Subjects:
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: None

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Abstract

Nowadays, new heterogeneous system technologies are flooding the market: through the past years, it is possible to observe the move from single CPUs to multi-core devices featuring CPUs, GPUs and large FPGAs, such as Xilinx Zynq-7000 or Zynq UltraScale+ MPSoC architectures. In this context, providing developers with transparent deployment capabilities to efficiently execute different applications on such complex devices is important. In this paper, a design flow that combines, on one side, PREESM, a dataflow-based prototyping framework and, on the other side, Xilinx SDSoC, an HLS-based framework to automatically generate and manage hardware accelerators, is presented. This integration leverages the automatic, static task scheduling obtained from PREESM with asynchronous invocations that trigger the parallel execution of multiple hardware accelerators from some of their associated sequential software threads. An image processing application is used as a proof of concept, showing the interoperability possibilities of both tools, the level of design automation achieved and, for the resulting computing architecture, the good performance scalability according to the number of accelerators and sw threads.

More information

Item ID: 51778
DC Identifier: http://oa.upm.es/51778/
OAI Identifier: oai:oa.upm.es:51778
DOI: 10.1109/ReCoSoC.2017.8016151
Deposited by: Alfonso Rodríguez Medina
Deposited on: 04 Sep 2018 07:05
Last Modified: 04 Sep 2018 07:05
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