A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures using PAPI

Suriano, Leonardo; Madroñal Quintín, Daniel; Rodriguez, Alfonso; Juarez, Eduardo; Sanz, Cesar y Torre Arnanz, Eduardo de la (2018). A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures using PAPI. En: "2018 13rd International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)", 9-11 Julio, Lille, France.

Descripción

Título: A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures using PAPI
Autor/es:
  • Suriano, Leonardo
  • Madroñal Quintín, Daniel
  • Rodriguez, Alfonso
  • Juarez, Eduardo
  • Sanz, Cesar
  • Torre Arnanz, Eduardo de la
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 2018 13rd International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Fechas del Evento: 9-11 Julio
Lugar del Evento: Lille, France
Título del Libro: 13rd International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Fecha: 11 Julio 2018
Materias:
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Licencias Creative Commons: Ninguna

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Resumen

In this work, a standard and unified method for monitoring hardware accelerators in Reconfigurable Computing Architectures is proposed, based on a standard software monitoring interface. The open source Performance Application Programming Interface (PAPI) library is commonly used in the field of High Performance Computing and aims at providing event information directly extracted from a set of Performance Monitor Counters. Important events such as data and instruction cache misses, hardware interrupts, etc. are collected to analyze and profile applications to pinpoint the contingent bottlenecks. In other words, it serves as a ”Hardware Abstraction layer” for applications running in the user-space. In this paper, its use is extended by proposing a method to target custom Performance Hardware Registers on accelerators built upon an FPGA. Furthermore, portability and standardization are discussed and the overhead associated with PAPI use is evaluated. Two hardware examples are proposed to evaluate this approach: a simple counter and an infrastructure for hardware accelerators called ARTICo3.

Más información

ID de Registro: 51783
Identificador DC: http://oa.upm.es/51783/
Identificador OAI: oai:oa.upm.es:51783
Depositado por: Alfonso Rodríguez Medina
Depositado el: 03 Sep 2018 11:37
Ultima Modificación: 03 Sep 2018 11:37
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