On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

Mora de Sambricio, Javier and Salvador Perea, Rubén and Torre Arnanz, Eduardo de la (2018). On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. "Genetic Programming and Evolvable Machines" ; pp. 1-32. ISSN 1573-7632. https://doi.org/10.1007/s10710-018-9340-5.

Description

Title: On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
Author/s:
  • Mora de Sambricio, Javier
  • Salvador Perea, Rubén
  • Torre Arnanz, Eduardo de la
Item Type: Article
Título de Revista/Publicación: Genetic Programming and Evolvable Machines
Date: 1 October 2018
ISSN: 1573-7632
Subjects:
Freetext Keywords: FPGA, Evolvable hardware, Dynamic partial reconfiguration, Systolic array, Cartesian genetic programming, Scalability
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: None

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Abstract

Evolvable hardware allows the generation of circuits that are adapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact, thus allowing large scale circuits to be implemented in a small FPGA area. This facilitates the use of these techniques in embedded systems with limited resources. The improvement on resource-efficient implementation techniques has allowed increasing the size of processing architectures from a few PEs to several hundreds. However, these large sizes pose new challenges for the EA and the architecture, which may not be able to take full advantage of the computing capabilities of its PEs. In this article, two different topologies—systolic array (SA) and Cartesian genetic programming (CGP)—are scaled from small to large sizes and analyzed, comparing their behavior and efficiency at different sizes. Additionally, improvements on SA connectivity are studied. Experimental results show that, in general, SA is considerably more resource-efficient than CGP, needing up to 60% fewer FPGA resources (LUTs) for a solution with similar performance, since the LUT usage per PE is 5 times smaller. Specifically, 10 × 10 SA has better performance than 5 × 10 CGP, but uses 50% fewer resources.

Funding Projects

TypeCodeAcronymLeaderTitle
Government of SpainTEC2014-58036-C4-2-RREBECCAUnspecifiedUnspecified
Government of SpainBES-2012-060459UnspecifiedUnspecifiedPrograma de becas FPI

More information

Item ID: 52974
DC Identifier: http://oa.upm.es/52974/
OAI Identifier: oai:oa.upm.es:52974
DOI: 10.1007/s10710-018-9340-5
Official URL: https://link.springer.com/article/10.1007%2Fs10710-018-9340-5
Deposited by: D. Javier Mora de Sambricio
Deposited on: 12 Nov 2018 07:44
Last Modified: 01 Oct 2019 22:30
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