Modelado y verificación de sistemas digitales con SystemVerilog

Koutsourais Fernández, Ana (2018). Modelado y verificación de sistemas digitales con SystemVerilog. Proyecto Fin de Carrera / Trabajo Fin de Grado, E.T.S.I. y Sistemas de Telecomunicación (UPM), Madrid.

Description

Title: Modelado y verificación de sistemas digitales con SystemVerilog
Author/s:
  • Koutsourais Fernández, Ana
Contributor/s:
  • Freire Rubio, Miguel Ángel
Item Type: Final Project
Degree: Grado en Ingeniería Electrónica de Comunicaciones
Date: 20 October 2018
Subjects:
Freetext Keywords: Sistemas digitales; Circuitos integrados
Faculty: E.T.S.I. y Sistemas de Telecomunicación (UPM)
Department: Ingeniería Telemática y Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

El objetivo principal de este proyecto es presentar la metodología de modelado y verificación con SystemVerilog, un lenguaje para la descripción y verificación de sistemas digitales (Hardware Description and Verification Language). La explicación de la aplicación del lenguaje está orientada a diseñadores con conocimientos de modelado VHDL. En primer lugar se describe el modelado de sistemas digitales con SystemVerilog. Se exponen las técnicas para modelar el funcionamiento de circuitos combinacionales, circuitos secuenciales y circuitos complejos. Después se explica la realización de bancos de test SystemVerilog para verificar el correcto funcionamiento de los modelos. A continuación se describe el lenguaje de especificación de propiedades de SystemVerilog (SVA, SystemVerilog Assertions), explicando la formulación de propiedades temporales y el uso de aserciones, mostrando ejemplos y un caso de aplicación sencillo. Para ilustrar la aplicación del modelado SystemVerilog se realiza el modelo de un master I2C, con el que se construye un circuito de medida de temperatura y humedad que se materializa en hardware con la tarjeta de prototipado DECA MAX10, que dispone de un sensor de temperatura y humedad (HDC1000, de Texas Instruments), y una tarjeta de expansión, XDECA, que se emplea para presentar las medidas. Abstract: The purpose of the present project is to introduce a Hardware Description Language called SystemVerilog, starting from some knowledge of VHDL language. The realization of the project consisted, first, in the study of the elements of SystemVerilog that are dedicate to model digital systems and the part which concerns the specification of temporary properties. On the first chapters of the present project, is going to be explained how to model and implement combinational logic and sequential circuits. In addition, how to verify this circuits using Test-Bench. Throughout the document is being described how to implement an application that measures through a temperature and humidity sensor (HDC1000, from Texas instruments). To develop the application it has been used the DECA prototype board, that includes the sensor with an I2C interface, and the XDECA expansion board. Furthermore, before describing how to implement the application, is going to be described the SystemVerilog Property Specification Language (SVA, SystemVerilog Assertions). This section explains the temporary properties and the use of assertions with a simple application example. To summarize, the project have two different sections, the first one is more a theoretical part that include the most important concepts to learn about how to implement the language SystemVerilog. The second part will develop the simulation and verification of the application. In our case, to do the verification of the measurement application, it will be used a tool called Quartus II.

More information

Item ID: 54817
DC Identifier: http://oa.upm.es/54817/
OAI Identifier: oai:oa.upm.es:54817
Deposited by: Biblioteca Universitaria Campus Sur
Deposited on: 29 Apr 2019 08:01
Last Modified: 29 Apr 2019 08:01
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