Accelerating the evolution of a systolic array-based evolvable hardware system

Mora de Sambricio, Javier and Torre Arnanz, Eduardo de la (2018). Accelerating the evolution of a systolic array-based evolvable hardware system. "Microprocessors and Microsystems", v. 56 ; pp. 144-156. ISSN 0141-9331. https://doi.org/10.1016/j.micpro.2017.12.001.

Description

Title: Accelerating the evolution of a systolic array-based evolvable hardware system
Author/s:
  • Mora de Sambricio, Javier
  • Torre Arnanz, Eduardo de la
Item Type: Article
Título de Revista/Publicación: Microprocessors and Microsystems
Date: February 2018
ISSN: 0141-9331
Volume: 56
Subjects:
Freetext Keywords: FPGA; Evolvable hardware; Dynamic partial reconfiguration; Evolutionary algorithm; Systolic array; LUT
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

Full text

[img] PDF - Users in campus UPM only until 1 March 2020 - Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader
Download (4MB)

Abstract

Evolvable hardware is a type of hardware that is able to adapt to different problems by going through a previous training stage which uses an evolutionary algorithm to find an optimized configuration. This configuration can be achieved through dynamic partial reconfiguration of an FPGA. Having a short time for the training stage is critical for the system to be able to adapt to changing conditions in real time. However, one of the problems of evolvable hardware based on dynamic partial reconfiguration is its long evolution time, mostly due to its slow reconfiguration speed. This can make such systems unsuitable for applications which require adaptation in a few seconds. Nevertheless, different reconfiguration and evolution techniques can substantially reduce the time taken by an evolvable hardware system to evolve for a specific problem. In this article, a system initially able to evolve in 8 minutes is optimized using multiple techniques (reconfiguration methodology, evolutionary algorithm optimization, and parallelization) so that it is able to obtain similar results in less than 2 s, achieving a speedup of near 300 times. Extensive experimental results prove the benefits of such techniques.

Funding Projects

TypeCodeAcronymLeaderTitle
Government of SpainTEC2014-58036-C4-2-RUnspecifiedUnspecifiedSistemas electrónicos empotrados confiables para control de ciudades bajo situaciones atípicas
Government of SpainBES-2012-060459UnspecifiedUnspecifiedUnspecified

More information

Item ID: 54982
DC Identifier: http://oa.upm.es/54982/
OAI Identifier: oai:oa.upm.es:54982
DOI: 10.1016/j.micpro.2017.12.001
Official URL: https://www.sciencedirect.com/science/article/pii/S0141933117305483?via%3Dihub
Deposited by: Memoria Investigacion
Deposited on: 14 May 2019 16:06
Last Modified: 14 May 2019 16:06
  • Logo InvestigaM (UPM)
  • Logo GEOUP4
  • Logo Open Access
  • Open Access
  • Logo Sherpa/Romeo
    Check whether the anglo-saxon journal in which you have published an article allows you to also publish it under open access.
  • Logo Dulcinea
    Check whether the spanish journal in which you have published an article allows you to also publish it under open access.
  • Logo de Recolecta
  • Logo del Observatorio I+D+i UPM
  • Logo de OpenCourseWare UPM