Pre-Calculated Duty Cycle Control Implemented in FPGA for Power Factor Correction

García Suárez, Oscar; García, Alejandro; Castro Martín, Ángel de y Azcondo, Francisco J. (2009). Pre-Calculated Duty Cycle Control Implemented in FPGA for Power Factor Correction. En: "35th Annual Conference of IEEE Industrial Electronics, 2009. IECON '09", 03/11/2009 - 05/11/2009, Oporto, Portugal. ISBN 978-1-4244-4650-6. https://doi.org/10.1109/IECON.2009.5415383.

Descripción

Título: Pre-Calculated Duty Cycle Control Implemented in FPGA for Power Factor Correction
Autor/es:
  • García Suárez, Oscar
  • García, Alejandro
  • Castro Martín, Ángel de
  • Azcondo, Francisco J.
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 35th Annual Conference of IEEE Industrial Electronics, 2009. IECON '09
Fechas del Evento: 03/11/2009 - 05/11/2009
Lugar del Evento: Oporto, Portugal
Título del Libro: Proceedings of the 35th Annual Conference of IEEE Industrial Electronics, 2009. IECON '09
Fecha: 2009
ISBN: 978-1-4244-4650-6
Materias:
Palabras Clave Informales: Power Factor Correction, Switched Mode Power Supply, Boost Converter, Field Programmable Gate Array, Digital Control.
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

A power factor correction (PFC) technique based on pre-calculated duty cycle values is presented in this paper. In this method the duty ratios for half a line period are calculated in advance and stored in a memory. By synchronizing the memory with the line, near unity power factors can be achieved in a specific operating point. The main advantage of this technique is that neither current measurement nor current loop are needed. To obtain stable output voltages a voltage loop is included. A boost converter prototype controlled by an FPGA evaluation board has been implemented in order to verify the functionality of the proposed method. Both the simulation and experimental results show that near unity power factor can be achieved with this PFC strategy.

Más información

ID de Registro: 5533
Identificador DC: http://oa.upm.es/5533/
Identificador OAI: oai:oa.upm.es:5533
Identificador DOI: 10.1109/IECON.2009.5415383
URL Oficial: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5415383
Depositado por: Memoria Investigacion
Depositado el: 20 Dic 2010 12:40
Ultima Modificación: 20 Abr 2016 14:19
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