A novel FPGA-based test-bench framework for SDI stream verification

Conti, Giuseppe and Kyrkou, Christos and Theocharides, Theocharis and Hernández-Peñaloza, Gustavo and Jiménez Bermejo, David (2020). A novel FPGA-based test-bench framework for SDI stream verification. "Eurasip Journal on Image And Video Processing" (n. 21); pp. 1-16. ISSN 1687-5281. https://doi.org/10.1186/s13640-020-00515-5.

Description

Title: A novel FPGA-based test-bench framework for SDI stream verification
Author/s:
  • Conti, Giuseppe
  • Kyrkou, Christos
  • Theocharides, Theocharis
  • Hernández-Peñaloza, Gustavo
  • Jiménez Bermejo, David
Item Type: Article
Título de Revista/Publicación: Eurasip Journal on Image And Video Processing
Date: July 2020
ISSN: 1687-5281
Subjects:
Freetext Keywords: Verification; FPGA; Video test-bench; Real-time system; Simulation
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Electrónica Física
Creative Commons Licenses: Recognition - No derivative works - Non commercial

Full text

[img]
Preview
PDF - Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader
Download (4MB) | Preview

Abstract

This paper presents a framework for complete simulation and verification of Serial Digital Interface (SDI) video using a verilog test-bench and geared toward FPGAs. This framework permits simulating the entire process: from test video signal generation to protocol verification in the FPGA which implements the Device Under Test (DUT). The novelty in the design is the combination of a customized test video signal generator with an implementation clone of DUT transceiver for in-depth protocol debugging. Identical input test patterns of the video protocol under test are generated and fed to DUT for verification. Thus, the model not only permits to evaluate the SDI transport layer but also validates the implementation at ultra low pixel level of the video format. This approach provides two advantages: cost saving in terms of additional lab test equipment and delivering all-in-one test solution to verify design and implementation. A practical implementation using a test example of a macroblock processing chain using SDI video interface shows the viability of the proposed framework for video protocol testing.

More information

Item ID: 65591
DC Identifier: http://oa.upm.es/65591/
OAI Identifier: oai:oa.upm.es:65591
DOI: 10.1186/s13640-020-00515-5
Official URL: https://jivp-eurasipjournals.springeropen.com/articles/10.1186/s13640-020-00515-5
Deposited by: Memoria Investigacion
Deposited on: 12 Dec 2020 08:55
Last Modified: 12 Dec 2020 08:55
  • Logo InvestigaM (UPM)
  • Logo GEOUP4
  • Logo Open Access
  • Open Access
  • Logo Sherpa/Romeo
    Check whether the anglo-saxon journal in which you have published an article allows you to also publish it under open access.
  • Logo Dulcinea
    Check whether the spanish journal in which you have published an article allows you to also publish it under open access.
  • Logo de Recolecta
  • Logo del Observatorio I+D+i UPM
  • Logo de OpenCourseWare UPM