Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems

Salvador Perea, Rubén; Moreno González, Félix Antonio; Riesgo Alcaide, Teresa y Sekanina, Lukás (2010). Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. "EURASIP Journal on Advances in Signal Processing", v. 2011 (n. 973806); pp. 1-20. ISSN 1687-6172. https://doi.org/10.1155/2011/973806.

Descripción

Título: Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems
Autor/es:
  • Salvador Perea, Rubén
  • Moreno González, Félix Antonio
  • Riesgo Alcaide, Teresa
  • Sekanina, Lukás
Tipo de Documento: Artículo
Título de Revista/Publicación: EURASIP Journal on Advances in Signal Processing
Fecha: Enero 2010
Volumen: 2011
Materias:
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

A bioinspired, evolutionary algorithm for optimizing wavelet transforms oriented to improve image compression in embedded systems is proposed, modelled, and validated here. A simplified version of an Evolution Strategy, using fixed point arithmetic and a hardware-friendly mutation operator, has been chosen as the search algorithm. Several cutdowns on the computing requirements have been done to the original algorithm, adapting it for an FPGA implementation. The work presented in this paper describes the algorithm as well as the test strategy developed to validate it, showing several results in the effort to find a suitable set of parameters that assure the success in the evolutionary search. The results show how high-quality transforms are evolved from scratch with limited precision arithmetic and a simplified algorithm. Since the intended deployment platform is an FPGA, HW/SW partitioning issues are also considered as well as code profiling accomplished to validate the proposal, showing some preliminary results of the proposed hardware architecture.

Más información

ID de Registro: 6848
Identificador DC: http://oa.upm.es/6848/
Identificador OAI: oai:oa.upm.es:6848
Identificador DOI: 10.1155/2011/973806
URL Oficial: http://www.hindawi.com/journals/asp/2011/973806/ref/
Depositado por: Memoria Investigacion
Depositado el: 06 May 2011 07:55
Ultima Modificación: 23 Feb 2017 17:32
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