Generic Systolic Array for Run-time Scalable Cores

Otero Marnotes, Andres; Esteves Krasteva, Yana; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2010). Generic Systolic Array for Run-time Scalable Cores. En: "6th International Symposium on Applied Reconfigurable Computing (ARC)", 17/03/2010 - 19/03/2010, Bangkok, Tailandia. ISBN 978-3-642-12132-6.

Descripción

Título: Generic Systolic Array for Run-time Scalable Cores
Autor/es:
  • Otero Marnotes, Andres
  • Esteves Krasteva, Yana
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 6th International Symposium on Applied Reconfigurable Computing (ARC)
Fechas del Evento: 17/03/2010 - 19/03/2010
Lugar del Evento: Bangkok, Tailandia
Título del Libro: Proceedings of the 6th International Symposium on Applied Reconfigurable Computing (ARC)
Fecha: 2010
ISBN: 978-3-642-12132-6
Volumen: 5992
Materias:
Palabras Clave Informales: Digital signal processing - adaptable cores - scalability - systolic array - partial runtime reconfiguration
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

This paper presents a scalable core architecture based on a generic systolic array. The size of this kind of cores can be adapted in real-time to cover changing application requirements or to the available area in a reconfigurable device. In this paper, the process of scaling the core is performed by the replication of a single processing element using run-time partial reconfiguration. Furthermore, rather than restricting the proposed solution to a given application, it is based on a generic systolic architecture which is adapted using a design flow which is also proposed. The paper includes a related work discussion, the proposal and definition of a systolic array communication approach, which does not require the use of specific macro structures and permits to achieve higher flexibility, and a design flow used to adapt the generic architecture. Further, the paper also includes an image filter application as a simple use case, along with implementation results for Virtex 5 FPGA.

Más información

ID de Registro: 7781
Identificador DC: http://oa.upm.es/7781/
Identificador OAI: oai:oa.upm.es:7781
URL Oficial: http://www.springerlink.com/content/r55pv6402v10761t/
Depositado por: Memoria Investigacion
Depositado el: 04 Ago 2011 09:27
Ultima Modificación: 20 Abr 2016 16:49
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