High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs

Salvador Perea, Rubén and Moreno González, Félix Antonio and Riesgo Alcaide, Teresa and Sekanina, Lukás (2010). High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs. In: "13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010", 01/09/2010 - 03/09/2010, Lille, Francia. ISBN 978-0-7695-4171-6.

Description

Title: High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs
Author/s:
  • Salvador Perea, Rubén
  • Moreno González, Félix Antonio
  • Riesgo Alcaide, Teresa
  • Sekanina, Lukás
Item Type: Presentation at Congress or Conference (Article)
Event Title: 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010
Event Dates: 01/09/2010 - 03/09/2010
Event Location: Lille, Francia
Title of Book: Proceedings of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010
Date: September 2010
ISBN: 978-0-7695-4171-6
Subjects:
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

The work reported in this paper describes the steps given towards an FPGA-based implementation of evolvable wavelet transforms for image compression in embedded systems. An Evolutionary Algorithm (EA) for the design and optimization of the transform coefficients is tailored for a suitable System on Chip implementation. Several cut downs on the computing requirements have been done to the original algorithm, adapting it for the FPGA implementation. What this paper addresses more specifically is the validation of the algorithm using fixed point arithmetic for the whole optimization process. The results show how high quality transforms are evolved from scratch with limited precision arithmetic. Also, preliminary results of the implementation in an FPGA device are included.

More information

Item ID: 7784
DC Identifier: http://oa.upm.es/7784/
OAI Identifier: oai:oa.upm.es:7784
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5615635&tag=1
Deposited by: Memoria Investigacion
Deposited on: 04 Aug 2011 08:21
Last Modified: 23 Feb 2017 17:41
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