Power analog to digital converter for voltage scaling applications

González Sánchez, Mª Carmen and Vasic, Miroslav and Alou Cervera, Pedro and García Suárez, Oscar and Oliver Ramírez, Jesús Angel and Cobos Márquez, José Antonio and Visairo Cruz, Horacio (2010). Power analog to digital converter for voltage scaling applications. In: "25th Annual IEEE Applied Power Electronics Conference and Exposition (APEC)", 21/02/2010 - 25/02/2010, Palm Springs, California, EEUU. ISBN 978-1-4244-4782-4.

Description

Title: Power analog to digital converter for voltage scaling applications
Author/s:
  • González Sánchez, Mª Carmen
  • Vasic, Miroslav
  • Alou Cervera, Pedro
  • García Suárez, Oscar
  • Oliver Ramírez, Jesús Angel
  • Cobos Márquez, José Antonio
  • Visairo Cruz, Horacio
Item Type: Presentation at Congress or Conference (Article)
Event Title: 25th Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
Event Dates: 21/02/2010 - 25/02/2010
Event Location: Palm Springs, California, EEUU
Title of Book: Proceedings of the 25th Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
Date: March 2010
ISBN: 978-1-4244-4782-4
Subjects:
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

In order to optimize energy efficiency, some applications require adapting supply voltage according to the work load requirements. For example, in high performance digital systems and in RF systems, voltage scaling and modulation techniques have been adopted in order to achieve a more efficient processing of the energy. These techniques are based in rapidly adjusting the system supply voltage level. In order to achieve this, a topology which is capable of achieving very fast changes of the output voltage is needed. In this paper a PWM multiphase topology whose phases are coupled by using transformers is proposed to be used in an envelope elimination and restoration (EER) technique. The proposed topology can achieve very fast changes between discrete voltage steps so it can be considered as a power analog to digital

More information

Item ID: 7816
DC Identifier: http://oa.upm.es/7816/
OAI Identifier: oai:oa.upm.es:7816
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5433659
Deposited by: Memoria Investigacion
Deposited on: 03 Aug 2011 08:00
Last Modified: 20 Apr 2016 16:50
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