Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Otero Marnotes, Andres; Torre Arnanz, Eduardo de la; Riesgo Alcaide, Teresa y Esteves Krasteva, Yana (2010). Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. En: "2010 International Conference Field Programmable Logic and Applications (FPL)", 31/08/2010 - 02/09/2010, Milán, Italia. ISBN 978-1-4244-7842-2.

Descripción

Título: Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
Autor/es:
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
  • Esteves Krasteva, Yana
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 2010 International Conference Field Programmable Logic and Applications (FPL)
Fechas del Evento: 31/08/2010 - 02/09/2010
Lugar del Evento: Milán, Italia
Título del Libro: Proceedings of 2010 International Conference Field Programmable Logic and Applications (FPL)
Fecha: 2010
ISBN: 978-1-4244-7842-2
Materias:
Palabras Clave Informales: Digital signal processing, adaptable cores, scalability, systolic array, partial runtime reconfiguration
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements of hardware IPs, functional scalability has been identified as an interesting feature. The proposal in this paper is to take advantage of the regularity and the high-processing capability of systolic arrays, to develop run-time functional scalable cores, making use of spatial scalability, by means of replicating and relocating basic processing elements of the array. The relocation process is performed using the dynamic-reconfiguration possibilities offered by commercial FPGAs. In this paper, an architectural template is proposed to develop systolic scalable coprocessors following this approach, together with its corresponding software drivers that may be executed within an embedded processor. In addition, a design flow is proposed to adapt the architectural template to different problems, together with some examples of scalable cores created following this design. This solution provides better results, regarding the reconfiguration time and the memory necessity overhead, compared with other dynamically scalable solutions

Más información

ID de Registro: 7817
Identificador DC: http://oa.upm.es/7817/
Identificador OAI: oai:oa.upm.es:7817
URL Oficial: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5694223&tag=1
Depositado por: Memoria Investigacion
Depositado el: 03 Ago 2011 07:37
Ultima Modificación: 20 Abr 2016 16:50
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