Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Esteves Krasteva, Yana (2010). Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. In: "2010 International Conference Field Programmable Logic and Applications (FPL)", 31/08/2010 - 02/09/2010, Milán, Italia. ISBN 978-1-4244-7842-2.

Description

Title: Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
Author/s:
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
  • Esteves Krasteva, Yana
Item Type: Presentation at Congress or Conference (Article)
Event Title: 2010 International Conference Field Programmable Logic and Applications (FPL)
Event Dates: 31/08/2010 - 02/09/2010
Event Location: Milán, Italia
Title of Book: Proceedings of 2010 International Conference Field Programmable Logic and Applications (FPL)
Date: 2010
ISBN: 978-1-4244-7842-2
Subjects:
Freetext Keywords: Digital signal processing, adaptable cores, scalability, systolic array, partial runtime reconfiguration
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements of hardware IPs, functional scalability has been identified as an interesting feature. The proposal in this paper is to take advantage of the regularity and the high-processing capability of systolic arrays, to develop run-time functional scalable cores, making use of spatial scalability, by means of replicating and relocating basic processing elements of the array. The relocation process is performed using the dynamic-reconfiguration possibilities offered by commercial FPGAs. In this paper, an architectural template is proposed to develop systolic scalable coprocessors following this approach, together with its corresponding software drivers that may be executed within an embedded processor. In addition, a design flow is proposed to adapt the architectural template to different problems, together with some examples of scalable cores created following this design. This solution provides better results, regarding the reconfiguration time and the memory necessity overhead, compared with other dynamically scalable solutions

More information

Item ID: 7817
DC Identifier: http://oa.upm.es/7817/
OAI Identifier: oai:oa.upm.es:7817
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5694223&tag=1
Deposited by: Memoria Investigacion
Deposited on: 03 Aug 2011 07:37
Last Modified: 20 Apr 2016 16:50
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