]>
The repository administrator has not yet configured an RDF license.
INVE_MEM_2008_59757.pdf
indexcodes.txt
lightbox.jpg
preview.jpg
medium.jpg
small.jpg
text/html
HTML Summary of #4318
Analytical High-level Power model for LUT-based
Components
Analytical High-level Power model for LUT-based
Components (PDF)
Analytical High-level Power model for LUT-based
Components (Other)
Analytical High-level Power model for LUT-based
Components (Other)
Analytical High-level Power model for LUT-based
Components (Other)
Analytical High-level Power model for LUT-based
Components (Other)
Analytical High-level Power model for LUT-based
Components (Other)
This paper presents an extended high-level model for logic power estimation of multipliers and adders implemented in FPGAs in the presence of glitching and correlation. The model is based on an analytical computation of the switching activity produced in the component and the FPGA implementation details of the component structure. It is extended to consider operands of different word-lengths, both zero-mean and non- zero mean signals, and the glitching produced inside the component, taking into account the sign nature of the autocorrelation coefficients of the componentsâ€™ inputs. The number of simulations needed for the model characterization is extremely small and can be reduced to only two. As the final power model is analytical, it is capable of providing power estimates in miliseconds. The results show that the mean relative error is within 10% of low-level power estimates given by the XPower tool.
5349
2009
Analytical High-level Power model for LUT-based
Components
Telecommunications
Telecomunicaciones
18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS'08
Lisboa, Portugal
Springer Verlag
Jevtic
Ruzica
Ruzica Jevtic
Carreras Vaquer
Carlos
Carlos Carreras Vaquer