2020-01-29T19:21:05Z
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oai:oa.upm.es:4339
2016-04-20T13:36:49Z
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An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithm
Echeverría Aramendi, Pedro
López Vallejo, Marisa
Mathematics
n this work we present an FPGA implementation of a single-precision °oating-point arith- metic powering unit. Our powering unit is based on an indirect method that transforms xy into a chain of operations involving a logarithm, a multiplication, an exponential function and dedicated logic for the case of a negative base. This approach allows to use the full input range for the base and exponent without limiting the range of the exponent as in direct methods. A tailored hardware implementation is exploited to increase the accuracy of the unit reducing the relative errors of the operations while high performance is obtained taking advantage of the FPGA capabilities for parallel architectures. A careful design of the pipeline stages of the involved operators allows a clock cycle of 201.3 MHz on a Xilinx Virtex-4 FPGA
E.T.S.I. Telecomunicación (UPM)
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
2008
info:eu-repo/semantics/conferenceObject
Presentation at Congress or Conference
Proceedings 8th Conference on Real Numbers and Computers (RNC8) | 8th Conference on Real Numbers and Computers (RNC8) | 07/07/2008-09/07/2008 | Santiago de Compostela, España
PeerReviewed
application/pdf
eng
http://www.ac.usc.es/rnc8/
info:eu-repo/semantics/openAccess
http://oa.upm.es/4339/