Items where author is "Otero Marnotes, Andres"

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Article

He, Wei and Bhasin, Shivam and Otero Marnotes, Andres and Graba, Tarik and Torre Arnanz, Eduardo de la and Danger, Jean-Luc (2015). Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. "IET Information Security", v. 9 (n. 1); pp. 1-13. ISSN 1751-8709. https://doi.org/10.1049/iet-ifs.2013.0058.

Portilla Berrueco, Jorge and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Stecklina, Oliver and Peter, S. and Langendörfer, Peter (2010). Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. "International Journal on Distributed Sensor Networks", v. 2011 ; pp. 1-12. ISSN 1550-1477. https://doi.org/10.1155/2010/740823.

Presentation at Congress or Conference

Zamacola, Rafael and García Martinez, Alberto and Mora de Sambricio, Javier and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la (2019). IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. In: "2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 3-5 diciembre 2018, Cancun, Mexico. https://doi.org/10.1109/RECONFIG.2018.8641703.

Mora de Sambricio, Javier and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2015). Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. In: "10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)", 29/06/2015 - 01/07/2015, Bremen, Germany. pp. 1-7. https://doi.org/10.1109/ReCoSoC.2015.7238087.

Gallego Galán, Ángel and Mora de Sambricio, Javier and Otero Marnotes, Andres and Salvador Perea, Rubén and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). A novel FPGA-based evolvable hardware system based on multiple processing arrays. In: "2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW)", 20/05/2013 - 21/05/2013, Cambridge, Massachusetts, EE.UU. pp. 182-191. https://doi.org/10.1109/IPDPSW.2013.56.

Gallego Galán, Ángel and Mora de Sambricio, Javier and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). A scalable evolvable hardware processing array. In: "Proceedings of International Conference on ReConFigurable Computing and FPGA (RECONFIG)", 09/12/2013 - 11/12/2013, Cancún (México). pp..

Gallego Galán, Ángel and Mora de Sambricio, Javier and Otero Marnotes, Andres and López, Blanca and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). A self-adaptive image processing application based on evolvable and scalable hardware. In: "23rd International Conference on Field Programmable Logic and Applications (FPL 2013)", 02/09/2013 - 04/09/2013, Porto, Portugal. pp.. https://doi.org/10.1109/FPL.2013.6645631.

Mora de Sambricio, Javier and Gallego Galán, Ángel and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. In: "Conference on Design and Architectures for Signal and Image Processing (DASIP)", 08/10/2013 - 10/10/2013, Cagliari, Italy. pp..

He, Wei and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic. In: "Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 05/12/2012 - 07/12/2012, Cancun (Mexico). ISBN 978-1-4673-2919-4. pp. 1-6.

Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. In: "Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 05/12/2012 - 07/12/2012, Cancun (Mexico). pp. 1-8.

Salvador Perea, Rubén and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Mora de Sambricio, Javier and Sekanina, Lukás (2012). Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration. In: "22nd International Conference on Field Programmable Logic and Applications (FPL2012)", 29/08/2012 - 31/08/2012, Oslo (Norway). ISBN 978-1-4673-2257-7. pp. 547-550.

Pilato, Christian and Cazzaniga, Andrea and Durelli, Gianluca and Otero Marnotes, Andres and Sciuto, Donatella and Santambrogio, Marco D. (2012). On the automatic integration of hardware accelerators into FPGA-based embedded systems. In: "Proceedings of 22nd International Conference on Field Programmable Logic and Applications (FPL)", 29/08/2012 - 31/08/2012, Oslo (Norway). ISBN 978-1-4673-2257-7. pp. 607-610.

Cervero, Teresa and Otero Marnotes, Andres and López, S. and Torre Arnanz, Eduardo de la and Gallicó, G. and Sarmiento, Roberto and Riesgo Alcaide, Teresa (2011). A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs. In: "2011 IEEE International Conference on Multimedia and Expo (ICME)", 11/07/2011 - 15/07/2011, Barcelona, España. ISBN 978-1-61284-348-3. pp. 1-6.

Otero Marnotes, Andres and Salvador Perea, Rubén and Mora, Javier and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Sekanina, Lukás (2011). A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems. In: "2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 06/06/2011 - 09/06/2011, San Diego (California, USA). ISBN 978-1-4577-0598-4. pp. 336-343.

Otero Marnotes, Andres and Llinás, M. and Lombardo, Miguel and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2011). Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs. In: "VLSI Circuits and Systems V", 18/04/2011 - 20/04/2011, Praga, República Checa. pp. 1-13.

Salvador Perea, Rubén and Otero Marnotes, Andres and Mora, Javier and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Sekanina, Lukás (2011). Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. In: "2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 06/06/2011 - 09/06/2011, San Diego, CA, EEUU. ISBN 978-1-4577-0598-4. pp. 184-191.

Salvador Perea, Rubén and Otero Marnotes, Andres and Mora, Javier and Torre Arnanz, Eduardo de la and Sekanina, Lukás and Riesgo Alcaide, Teresa (2011). Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. In: "2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)", 30/11/2011 - 02/12/2011, Cancú, México. ISBN 978-1-4577-1734-5. pp. 164-169.

Cervero, Teresa and Otero Marnotes, Andres and López, S. and Torre Arnanz, Eduardo de la and Gallicó, G. and Riesgo Alcaide, Teresa and Sarmiento, Roberto (2011). Framework adaptable y reconfigurable dinámicamente para procesamiento de vídeo: aplicación a la etapa de filtrado adaptativo en sistemas de compresión de vídeo H.264/AVC y SVC. In: "XI Jornadas de Computación Reconfigurable y Aplicaciones(JCRA) 2011", 07/09/2011 - 09/09/2011, La Laguna, Tenerife, España. ISBN 9788461488148. pp. 1-6.

Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Cervero, Teresa and López, S. and Gallicó, G. and Sarmiento, Roberto (2011). Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. In: "21st International Conference on Field Programmable Logic and Applications", 05/09/2011 - 07/09/2011, Creta, Grecia. ISBN 978-1-4577-1484-9. pp. 1-6.

Otero Marnotes, Andres and Morales Cas, Angel and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2010). A Modular Peripheral to Support Self-Reconfiguration in SoCs. In: "13th Euromicro Conference On Digital System Desig (DSD)", 01/09/2010 - 03/09/2010, Lille, Francia.

Otero Marnotes, Andres and Esteves Krasteva, Yana and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2010). Generic Systolic Array for Run-time Scalable Cores. In: "6th International Symposium on Applied Reconfigurable Computing (ARC)", 17/03/2010 - 19/03/2010, Bangkok, Tailandia. ISBN 978-3-642-12132-6.

Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Esteves Krasteva, Yana (2010). Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. In: "2010 International Conference Field Programmable Logic and Applications (FPL)", 31/08/2010 - 02/09/2010, Milán, Italia. ISBN 978-1-4244-7842-2.

Thesis

Otero Marnotes, Andres (2014). Run-Time Scalable Hardware for Reconfigurable Systems. Thesis (Doctoral), E.T.S.I. Industriales (UPM).

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