Items where Author is "Torre Arnanz, Eduardo de la"

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Article

Mora de Sambricio, Javier and Salvador Perea, Rubén and Torre Arnanz, Eduardo de la (2018). On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. "Genetic Programming and Evolvable Machines" ; pp. 1-32. ISSN 1573-7632. https://doi.org/10.1007/s10710-018-9340-5.

Mora de Sambricio, Javier and Torre Arnanz, Eduardo de la (2018). Accelerating the evolution of a systolic array-based evolvable hardware system. "Microprocessors and Microsystems", v. 56 ; pp. 144-156. ISSN 0141-9331. https://doi.org/10.1016/j.micpro.2017.12.001.

Cumplido, René and Torre Arnanz, Eduardo de la and Feregrino-Uribe, Claudia and Wirthlin, Michael (2015). Introduction to Special issue on Reconfigurable computing and FPGAs. "Microprocessors and Microsystems", v. 39 (n. 7); pp. 541-542. ISSN 0141-9331. https://doi.org/10.1016/j.micpro.2015.08.006.

He, Wei and Bhasin, Shivam and Otero Marnotes, Andres and Graba, Tarik and Torre Arnanz, Eduardo de la and Danger, Jean-Luc (2015). Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. "IET Information Security", v. 9 (n. 1); pp. 1-13. ISSN 1751-8709. https://doi.org/10.1049/iet-ifs.2013.0058.

Portilla Berrueco, Jorge and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Stecklina, Oliver and Peter, S. and Langendörfer, Peter (2010). Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. "International Journal on Distributed Sensor Networks", v. 2011 ; pp. 1-12. ISSN 1550-1477. https://doi.org/10.1155/2010/740823.

Presentation at Congress or Conference

Zamacola, Rafael and García Martinez, Alberto and Mora de Sambricio, Javier and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la (2019). IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. In: "2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 3-5 diciembre 2018, Cancun, Mexico. https://doi.org/10.1109/RECONFIG.2018.8641703.

Palumbo, F. and Torre Arnanz, Eduardo de la (2018). Self-Adaptivity in heterogeneous CPS platforms. In: "CPS Summer School 2018 Designing Cyber-Physical Systems – From concepts to implementation", 17 - 21 September, 2018, Alghero (Italia). pp. 1-53.

Suriano, Leonardo and Madroñal Quintín, Daniel and Rodriguez, Alfonso and Juarez, Eduardo and Sanz, Cesar and Torre Arnanz, Eduardo de la (2018). A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures using PAPI. In: "2018 13rd International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)", 9-11 Julio, Lille, France.

Fanni, Tiziana and Rodríguez Medina, Alfonso and Sau, Carlo and Suriano, Leonardo and Palumbo, F. and Raffo, L. and Torre Arnanz, Eduardo de la (2018). Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems. In: "2018 International Conference on Reconfigurable Computing and FPGAs (ReConFig18)", December 3-5, 2018, Cancun, Mexico. ISBN 978-1-7281-1968-7. pp. 1-8.

Torre Arnanz, Eduardo de la (2018). Self-Adaptation of Cyber Physical Systems: Flexible HW/SW computing. In: "CPS Summer School 2018 Designing Cyber-Physical Systems – From concepts to implementation", 17 - 21 September, 2018, Alghero (Italia). pp. 1-7.

Suriano, Leonardo and Rodriguez, Alfonso and Desnos, Karol and Pelcat, Maxime and Torre Arnanz, Eduardo de la (2017). Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC. In: "2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)", 12-14 Julio 2017, Madrid, Spain. https://doi.org/10.1109/ReCoSoC.2017.8016151.

Masin, M. and Palumbo, F. and Myrhaug, H. and Oliveira Filho, J. A. and Pastena, M. and Pelcat, Maxime and Raffo, L. and Regazzoni, F. and Sanchez, A. A. and Toffetti, A. and Torre Arnanz, Eduardo de la and Zedda, Katiusca (2017). Cross-layer Design of Reconfigurable Cyber-Physical Systems. In: "2017 Design, Automation & Test in Europe (DATE)", March 27 to 31, 2017, Laussane, Suiza. ISBN 978-3-9815370-9-3. pp. 740-745. https://doi.org/10.23919/DATE.2017.7927088.

Pérez, Arturo and Suriano, Leonardo and Otero, Andrés and Torre Arnanz, Eduardo de la (2017). Dynamic Reconfiguration under RTEMS for Fault Mitigation and Functional Adaptation in SRAM-based SoPCs for Space Systems. In: "2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 24-27 July 2017, Pasadena, CA, USA. pp. 40-47. https://doi.org/10.1109/AHS.2017.8046357.

He, Wei and Stottinger, Marc and Torre Arnanz, Eduardo de la and Díaz, Verónica (2015). A Self-Tuned Thermal Compensation System for Reducing Process Variation Influence in Side-Channel Attack Resistant Dual-Rail Logic. In: "2015 Conference on Design of Circuits and Integrated Systems (DCIS 2015)", 25-27 November 2015, Estoril (Portugal). ISBN 978-1-4673-7228-2. pp. 1-8.

Veljković, Filip and Riesgo Alcaide, Teresa and Torre Arnanz, Eduardo de la (2015). Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. In: "NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015)", 15/06/2015 - 18/06/2015, Montreal, Canadá. pp. 1-8. https://doi.org/10.1109/AHS.2015.7231165.

Rodríguez Medina, Alfonso and Valverde Alcalá, Juan and Torre Arnanz, Eduardo de la (2015). Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. In: "International Conference on ReConFigurable Computing and FPGAs (ReConFig 2015)", 07/12/2015 - 9/12/2015, Bremen, Germany. pp. 1-8. https://doi.org/10.1109/ReConFig.2015.7393297.

Rodríguez Medina, Alfonso and Valverde Alcalá, Juan and Castañares Franco, César and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2015). Execution modeling in self-aware FPGA-based architectures for efficient resource management. In: "10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)", 29/06/2015 - 01/07/2015, Bremen, Germany. pp. 1-8. https://doi.org/10.1109/ReCoSoC.2015.7238086.

Mora de Sambricio, Javier and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2015). Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. In: "10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)", 29/06/2015 - 01/07/2015, Bremen, Germany. pp. 1-7. https://doi.org/10.1109/ReCoSoC.2015.7238087.

Rodríguez Medina, Alfonso and Valverde Alcalá, Juan and Castañares Franco, César and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2015). Live Demonstration: A Dynamically Adaptable Image Processing Application Running in an FPGA-Based WSN Platform. In: "IEEE International Symposium on Published in: Circuits and Systems (ISCAS 2015)", 24/05/2015 - 27/05/2017, Lisbon, Portugal. pp. 1902-1908. https://doi.org/10.1109/ISCAS.2015.7169035.

Valverde Alcalá, Juan and Rodríguez, A. and Camarero, J.J. and Otero, A. and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems. In: "24th International Conference on Field Programmable Logic and Applications", September 1 - 5, 2014, Munich (Germany). pp. 1-4.

Valverde Alcalá, Juan and Rodríguez Medina, Alfonso and Mora de Sambricio, Javier and Castañares Franco, César and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time. In: "2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)", 08-10 oct 2014, Madrid (Spain). pp. 1-2.

Veljković, Filip and Riesgo Alcaide, Teresa and Torre Arnanz, Eduardo de la and Regada, Raúl and Berrojo, Luis (2014). A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. In: "2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 14/07/2014 17/07/2014, Leicester, United Kingdom. pp. 143-150. https://doi.org/10.1109/AHS.2014.6880170.

Veljković, Filip and Riesgo Alcaide, Teresa and Berrojo, Luis and Regada, Raúl and Álvaro Castellanos, Ángel de and Torre Arnanz, Eduardo de la (2014). Analysis of design alternatives on using dynamic and partial reconfiguration in a space application. In: "Data Systems in Aerospace (DASIA 2014)", 03/06/2014 - 05/06/2014, Warsaw, Poland. pp. 1-7.

Vázquez Antolín, Javier and López, Blanca and Valverde Alcalá, Juan and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). Collaborative Evolution Strategies on Evolvable Hardware Networked Elements. In: "2014 Conference on Design of Circuits and Integrated Circuits (DCIS)", 26-28 nov 2014, Madrid (Spain). pp. 1-5.

López, Blanca and Mora, Javier and Mansanet, Pablo and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). Development of Brain-Computer Interfaces using Evolvable Hardware. In: "2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)", 08-10 oct 2014, Madrid (Spain). ISBN 979-10-92279-06-1. p. 1.

Rodríguez Medina, Alfonso and Valverde Alcalá, Juan and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). Dynamic management of multikernel multithread accelerators using dynamic partial reconfiguration. In: "9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC 2014)", 26/05/2014 - 28/05/2014, Montpellier, France. pp. 1-7. https://doi.org/10.1109/ReCoSoC.2014.6861363.

Mora de Sambricio, Javier and Gallego Galán, Ángel and Otero, Andrés and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). Increased fault tolerance in evolvable hardware through automatic upscaling. In: "Conference on Design and Architectures for Signal and Image Processing (DASIP 2014)", 08/10/2014 - 10/10/2014, Madrid, Spain. p. 1.

López, Blanca and Valverde Alcalá, Juan and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2014). Power-Aware Multi-Objective Evolvable Hardware System on an FPGA. In: "2014 NASA/ESA Conference on Adaptive Hardware and Systems", July 14 - 18, 2014, Leicester (United Kingdom). ISBN 978-1-4799-5356-1. pp. 61-68.

Vaskova, Anna and Portela-Garcia, Marta and Garcia-Valderas, Mario and Lopez-Ongil, Celia and Portilla Berrueco, Jorge and Valverde Alcalá, Juan and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). Hardening digital systems with distributed functionality: robust networks. In: "VLSI Circuits and Systems VI - SPIE Proceedings Microtechnologies 2013", 24/04/2013 - 26/04/2013, Grenoble (France).

Gallego Galán, Ángel and Mora de Sambricio, Javier and Otero Marnotes, Andres and Salvador Perea, Rubén and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). A novel FPGA-based evolvable hardware system based on multiple processing arrays. In: "2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW)", 20/05/2013 - 21/05/2013, Cambridge, Massachusetts, EE.UU. pp. 182-191. https://doi.org/10.1109/IPDPSW.2013.56.

Gallego Galán, Ángel and Mora de Sambricio, Javier and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). A scalable evolvable hardware processing array. In: "Proceedings of International Conference on ReConFigurable Computing and FPGA (RECONFIG)", 09/12/2013 - 11/12/2013, Cancún (México). pp..

Gallego Galán, Ángel and Mora de Sambricio, Javier and Otero Marnotes, Andres and López, Blanca and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). A self-adaptive image processing application based on evolvable and scalable hardware. In: "23rd International Conference on Field Programmable Logic and Applications (FPL 2013)", 02/09/2013 - 04/09/2013, Porto, Portugal. pp.. https://doi.org/10.1109/FPL.2013.6645631.

Mora de Sambricio, Javier and Gallego Galán, Ángel and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2013). Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. In: "Conference on Design and Architectures for Signal and Image Processing (DASIP)", 08/10/2013 - 10/10/2013, Cagliari, Italy. pp..

He, Wei and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. In: "Third International Workshop, COSADE 2012,", 03/05/2012 - 04/05/2012, Darmstadt, Alemania. ISBN 978-3-642-29911-7. pp. 39-53.

He, Wei and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic. In: "Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 05/12/2012 - 07/12/2012, Cancun (Mexico). ISBN 978-1-4673-2919-4. pp. 1-6.

Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. In: "Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 05/12/2012 - 07/12/2012, Cancun (Mexico). pp. 1-8.

Salvador Perea, Rubén and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Mora de Sambricio, Javier and Sekanina, Lukás (2012). Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration. In: "22nd International Conference on Field Programmable Logic and Applications (FPL2012)", 29/08/2012 - 31/08/2012, Oslo (Norway). ISBN 978-1-4673-2257-7. pp. 547-550.

Lombardo, Miguel and Camarero, Julio and Valverde Alcalá, Juan and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). Power management techniques in an FPGA-Based WSN node for high performance application. In: "7th International Workshop Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)", 09/07/2012 - 11/07/2012, York, United Kingdom. pp. 1-5.

Cervero, Teresa and Otero Marnotes, Andres and López, S. and Torre Arnanz, Eduardo de la and Gallicó, G. and Sarmiento, Roberto and Riesgo Alcaide, Teresa (2011). A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs. In: "2011 IEEE International Conference on Multimedia and Expo (ICME)", 11/07/2011 - 15/07/2011, Barcelona, España. ISBN 978-1-61284-348-3. pp. 1-6.

Otero Marnotes, Andres and Salvador Perea, Rubén and Mora, Javier and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Sekanina, Lukás (2011). A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems. In: "2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 06/06/2011 - 09/06/2011, San Diego (California, USA). ISBN 978-1-4577-0598-4. pp. 336-343.

He, Wei and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2011). A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. In: "2011 International Conference on Reconfigurable Computing and FPGAs, RECONFIG '11", 30/11/2011 - 02/12/2011, Cancú, México. ISBN 978-0-7695-4551-6.

Otero Marnotes, Andres and Llinás, M. and Lombardo, Miguel and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2011). Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs. In: "VLSI Circuits and Systems V", 18/04/2011 - 20/04/2011, Praga, República Checa. pp. 1-13.

Salvador Perea, Rubén and Otero Marnotes, Andres and Mora, Javier and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Sekanina, Lukás (2011). Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. In: "2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 06/06/2011 - 09/06/2011, San Diego, CA, EEUU. ISBN 978-1-4577-0598-4. pp. 184-191.

Salvador Perea, Rubén and Otero Marnotes, Andres and Mora, Javier and Torre Arnanz, Eduardo de la and Sekanina, Lukás and Riesgo Alcaide, Teresa (2011). Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. In: "2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)", 30/11/2011 - 02/12/2011, Cancú, México. ISBN 978-1-4577-1734-5. pp. 164-169.

Cervero, Teresa and Otero Marnotes, Andres and López, S. and Torre Arnanz, Eduardo de la and Gallicó, G. and Riesgo Alcaide, Teresa and Sarmiento, Roberto (2011). Framework adaptable y reconfigurable dinámicamente para procesamiento de vídeo: aplicación a la etapa de filtrado adaptativo en sistemas de compresión de vídeo H.264/AVC y SVC. In: "XI Jornadas de Computación Reconfigurable y Aplicaciones(JCRA) 2011", 07/09/2011 - 09/09/2011, La Laguna, Tenerife, España. ISBN 9788461488148. pp. 1-6.

Liang, Guixuan and He, Danping and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2011). Low-power, high-speed FFT processor for MB-OFDM UWB application. In: "Microtechnologies for the New Millennium 2011 (SPIE)", 18/04/2011 - 22/04/2011, Praga, República Checa. pp. 1-13.

Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Cervero, Teresa and López, S. and Gallicó, G. and Sarmiento, Roberto (2011). Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. In: "21st International Conference on Field Programmable Logic and Applications", 05/09/2011 - 07/09/2011, Creta, Grecia. ISBN 978-1-4577-1484-9. pp. 1-6.

He, Wei and Pizarro, Carlos and Torre Arnanz, Eduardo de la and Portilla Berrueco, Jorge and Riesgo Alcaide, Teresa (2011). SCA security verification on wireless sensor network node. In: "Microtechnologies for the New Millennium 2011 (SPIE)", 18/04/2011 - 22/04/2011, Praga, República Checa. pp. 1-15.

Otero Marnotes, Andres and Morales Cas, Angel and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2010). A Modular Peripheral to Support Self-Reconfiguration in SoCs. In: "13th Euromicro Conference On Digital System Desig (DSD)", 01/09/2010 - 03/09/2010, Lille, Francia.

Isturiz, Aitor and Viñals, Javier and Fernandez, Santiago and Basagoiti, Rosa and Torre Arnanz, Eduardo de la and Novo, Justo (2010). Development of an aeronautical electromechanical actuator with real time health monitoring capability. In: "4th International Conference on Recent Advances in Aerospace Actuation Systems and Components, 2010 (R3ASC)", 05/05/2010 - 07/05/2010, Toulouse (France).

Otero Marnotes, Andres and Esteves Krasteva, Yana and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2010). Generic Systolic Array for Run-time Scalable Cores. In: "6th International Symposium on Applied Reconfigurable Computing (ARC)", 17/03/2010 - 19/03/2010, Bangkok, Tailandia. ISBN 978-3-642-12132-6.

Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Esteves Krasteva, Yana (2010). Run-time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. In: "2010 International Conference Field Programmable Logic and Applications (FPL)", 31/08/2010 - 02/09/2010, Milán, Italia. ISBN 978-1-4244-7842-2.

Steffen, Peter and Oliver, Stecklina and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Langendörfer, Peter and Riesgo Alcaide, Teresa (2009). Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes. In: "6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09", 22/06/2009 - 26/06/2009, Roma, Italia. ISBN 978-1-4244-3938-6.

Vladimir, Matev and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2009). Method for run time hardware code profiling for algorithm acceleration. In: "VLSI Circuits and Systems IV", 01/05/2009 - 03/05/2009, Dresden, Alemania. ISBN 9780819476371.

Esteves Krasteva, Yana and Portilla Berrueco, Jorge and Tobajas Guerrero, Felix and Torre Arnanz, Eduardo de la (2009). Using Partial Reconfiguration for SoC Design and Implementation. In: "VLSI Circuits and Systems IV", 01/05/2009 - 03/05/2009, Dresden, Alemania. ISBN 9780819476371.

Esteves Krasteva, Yana and Criado, Francisco and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2009). NoC Emulation based on Partial Reconfiguration. In: "XXIII International Conference on Design of Circuits and Integrated Systems (DCIS'2008)", 12/11/2008-14/11/2008, Grenoble, Francia. ISBN 978-28-4813-124-5. p. 36.

Esteves Krasteva, Yana and Criado, Francisco and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2008). A Fast Emulation-Based NoC Prototyping Framework. In: "International Conference on ReConFigurable Computing and FPGAs (ReConFig'08)", 03/12/2008-05/12/2008, Cancún, México. ISBN 978-1-4244-3748-1. pp. 211-216.

Esteves Krasteva, Yana and Portilla Berrueco, Jorge and Carnicer, Jose María and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2008). Remote HW-SW Reconfigurable Wireless Sensor Nodes. In: "34th Annual Conference of the IEEE Industrial Electronics Society. IECON-2008", 10/11/2008-13/11/2008, Orlando, Florida, USA. ISBN 978-14-2441-766-7. pp..

Esteves Krasteva, Yana and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2008). Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation. In: "34th Annual Conference of the IEEE Industrial Electronics Society. IECON-2008", 10/11/2008-13/11/2008, Orlando, Florida, USA. ISBN 978-1-4244-1766-7. pp..

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