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Fernandez, M.J. and Carro Liñares, Manuel and Hermenegildo, Manuel V. (1996). IDRA (IDeal Resource Allocation): Computing ideal speedups in parallel logic programming. In: "Second International Euro-Par Conference", August 26-29, 1996, Lyon, France. ISBN 9783540616276.
Title: | IDRA (IDeal Resource Allocation): Computing ideal speedups in parallel logic programming |
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Author/s: |
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Item Type: | Presentation at Congress or Conference (Article) |
Event Title: | Second International Euro-Par Conference |
Event Dates: | August 26-29, 1996 |
Event Location: | Lyon, France |
Title of Book: | Euro-Par'96 Parallel Processing |
Date: | August 1996 |
ISBN: | 9783540616276 |
Volume: | 1124 |
Subjects: | |
Freetext Keywords: | Parallel logic programming, Simulation, Parallelism, Concurrency,Performance evaluation, Programación lógica paralela, Simulación, Paralelismo, Concurrencia, Evaluación de resultados. |
Faculty: | Facultad de Informática (UPM) |
Department: | Inteligencia Artificial |
Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
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We present a technique to estimate accurate speedups for parallel logic programs with relative independence from characteristics of a given implementation or underlying parallel hardware. The proposed technique is based on gathering accurate data describing one execution at run-time, which is fed to a simulator. Alternative schedulings are then simulated and estimates computed for the corresponding speedups. A tool implementing the aforementioned techniques is presented, and its predictions are compared to the performance of real systems, showing good correlation.
Item ID: | 14419 |
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DC Identifier: | https://oa.upm.es/14419/ |
OAI Identifier: | oai:oa.upm.es:14419 |
Official URL: | http://link.springer.com/chapter/10.1007%2FBFb0024769?LI=true |
Deposited by: | Biblioteca Facultad de Informatica |
Deposited on: | 05 Feb 2013 19:56 |
Last Modified: | 21 Apr 2016 14:04 |