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High Performance FPGA-oriented mersenne twister uniform random number generator
Citation
Echeverría Aramendi, Pedro and López Vallejo, Marisa (2013). High Performance FPGA-oriented mersenne twister uniform random number generator. "Journal of Signal Processing Systems", v. 71 (n. 2); pp. 105-109. ISSN 1939-8018. https://doi.org/10.1007/s11265-012-0684-4.
Description
| Title: | High Performance FPGA-oriented mersenne twister uniform random number generator |
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| Author/s: |
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| Item Type: | Article |
| Título de Revista/Publicación: | Journal of Signal Processing Systems |
| Date: | May 2013 |
| ISSN: | 1939-8018 |
| Volume: | 71 |
| Subjects: | |
| Freetext Keywords: | Mersenne-Twister URNG, FPGA, Monte Carlo |
| Faculty: | E.T.S.I. Telecomunicación (UPM) |
| Department: | Ingeniería Electrónica |
| Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
Abstract
Mersenne Twister (MT) uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical table-based architecture, a different architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures has been proven in a high performance Gaussian RNG.
More information
| Item ID: | 16695 |
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| DC Identifier: | https://oa.upm.es/16695/ |
| OAI Identifier: | oai:oa.upm.es:16695 |
| DOI: | 10.1007/s11265-012-0684-4 |
| Official URL: | http://link.springer.com/article/10.1007%2Fs11265-... |
| Deposited by: | Memoria Investigacion |
| Deposited on: | 04 Aug 2013 08:13 |
| Last Modified: | 21 Apr 2016 17:03 |
