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On the automatic integration of hardware accelerators into FPGA-based embedded systems
Citation
Pilato, Christian and Cazzaniga, Andrea and Durelli, Gianluca and Otero Marnotes, Andres and Sciuto, Donatella and Santambrogio, Marco D. (2012). On the automatic integration of hardware accelerators into FPGA-based embedded systems. In: "Proceedings of 22nd International Conference on Field Programmable Logic and Applications (FPL)", 29/08/2012 - 31/08/2012, Oslo (Norway). ISBN 978-1-4673-2257-7. pp. 607-610.
Description
| Title: | On the automatic integration of hardware accelerators into FPGA-based embedded systems |
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| Author/s: |
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| Item Type: | Presentation at Congress or Conference (Article) |
| Event Title: | Proceedings of 22nd International Conference on Field Programmable Logic and Applications (FPL) |
| Event Dates: | 29/08/2012 - 31/08/2012 |
| Event Location: | Oslo (Norway) |
| Title of Book: | Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on |
| Date: | 2012 |
| ISBN: | 978-1-4673-2257-7 |
| Subjects: | |
| Faculty: | Centro de Electrónica Industrial (CEI) (UPM) |
| Department: | Otro |
| Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
Abstract
This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code.
More information
| Item ID: | 20875 |
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| DC Identifier: | https://oa.upm.es/20875/ |
| OAI Identifier: | oai:oa.upm.es:20875 |
| Official URL: | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6339218 |
| Deposited by: | Memoria Investigacion |
| Deposited on: | 19 Nov 2013 18:39 |
| Last Modified: | 22 Sep 2014 11:21 |
