Wake-up architecture for Wireless sensor nodes based on ultra low power FPGA

Roselló Gómez-Lobo, Víctor Julián and Portilla Berrueco, Jorge and Riesgo Alcaide, Teresa (2012). Wake-up architecture for Wireless sensor nodes based on ultra low power FPGA. In: "9th European Conference on Wireless Sensor Networks (EWSN 2012)", 15/02/2012 - 17/02/2012, Trento (Italia). pp. 1-2.

Description

Title: Wake-up architecture for Wireless sensor nodes based on ultra low power FPGA
Author/s:
  • Roselló Gómez-Lobo, Víctor Julián
  • Portilla Berrueco, Jorge
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Poster)
Event Title: 9th European Conference on Wireless Sensor Networks (EWSN 2012)
Event Dates: 15/02/2012 - 17/02/2012
Event Location: Trento (Italia)
Title of Book: EWSN 2012 Europena Workshop on Sensor NEtworks
Date: 2012
Subjects:
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Otro
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

In this work a novel wake-up architecture for wireless sensor nodes based on ultra low power FPGA is presented. A simple wake up messaging mechanism for data gathering applications is proposed. The main goal of this work is to evaluate the utilization of low power configurable devices to take advantage of their speed, flexibility and low power consumption compared with traditional approaches, based on ASICs or microcontrollers, for frame decoding and data control. A test bed based on infrared communications has been built to validate the messaging mechanism and the processing architecture.

More information

Item ID: 20954
DC Identifier: https://oa.upm.es/20954/
OAI Identifier: oai:oa.upm.es:20954
Official URL: http://ewsn12.disi.unitn.it/
Deposited by: Memoria Investigacion
Deposited on: 20 Nov 2013 18:19
Last Modified: 21 Apr 2016 11:03
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