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A hardware mechanism to reduce the energy consumption of the register file of in-order architectures
Citation
Ayala Rodrigo, José Luis and López Vallejo, Marisa and López Barrio, Carlos Alberto and Veidenbaum, Alexander (2008). A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. "International Journal of Embedded Systems", v. 3 (n. 4); pp. 285-293. ISSN 1741-1076. https://doi.org/10.1504/IJES.2008.022400.
Description
| Title: | A hardware mechanism to reduce the energy consumption of the register file of in-order architectures |
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| Author/s: |
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| Item Type: | Article |
| Título de Revista/Publicación: | International Journal of Embedded Systems |
| Date: | July 2008 |
| ISSN: | 1741-1076 |
| Volume: | 3 |
| Subjects: | |
| Freetext Keywords: | register file; in-order; power reduction; predecode; hardware approach. |
| Faculty: | E.T.S.I. Telecomunicación (UPM) |
| Department: | Ingeniería Electrónica |
| Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
Abstract
This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.
More information
| Item ID: | 2785 |
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| DC Identifier: | https://oa.upm.es/2785/ |
| OAI Identifier: | oai:oa.upm.es:2785 |
| DOI: | 10.1504/IJES.2008.022400 |
| Deposited by: | Memoria Investigacion |
| Deposited on: | 08 Apr 2010 10:41 |
| Last Modified: | 20 Apr 2016 12:26 |
