A scalable evolvable hardware processing array

Gallego Galán, Ángel, Mora de Sambricio, Javier, Otero Marnotes, Andres, Torre Arnanz, Eduardo de la ORCID: https://orcid.org/0000-0001-5697-0573 and Riesgo Alcaide, Teresa ORCID: https://orcid.org/0000-0003-0532-8681 (2013). A scalable evolvable hardware processing array. In: "Proceedings of International Conference on ReConFigurable Computing and FPGA (RECONFIG)", 09/12/2013 - 11/12/2013, Cancún (México). pp..

Description

Title: A scalable evolvable hardware processing array
Author/s:
  • Gallego Galán, Ángel
  • Mora de Sambricio, Javier
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la https://orcid.org/0000-0001-5697-0573
  • Riesgo Alcaide, Teresa https://orcid.org/0000-0003-0532-8681
Item Type: Presentation at Congress or Conference (Article)
Event Title: Proceedings of International Conference on ReConFigurable Computing and FPGA (RECONFIG)
Event Dates: 09/12/2013 - 11/12/2013
Event Location: Cancún (México)
Date: 2013
Subjects:
Freetext Keywords: Evolvable hardware,scalability,dynamic and partial reconfiguration,FPGAs
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Otro
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits self-adaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit are an example. Also, thanks to DPR, these systems can be provided with scalability, a feature that allows a system to change the number of allocated resources at run-time in order to vary some feature, such as performance. The combination of both aspects leads to scalable evolvable hardware (SEH), which changes in size as an extra degree of freedom when trying to achieve the optimal solution by means of evolution. The main contributions of this paper are an architecture of a scalable and evolvable hardware processing array system, some preliminary evolution strategies which take scalability into consideration, and to show in the experimental results the benefits of combined evolution and scalability. A digital image filtering application is used as use case.

More information

Item ID: 30248
DC Identifier: https://oa.upm.es/30248/
OAI Identifier: oai:oa.upm.es:30248
Deposited by: Memoria Investigacion
Deposited on: 26 Apr 2015 07:37
Last Modified: 25 May 2015 14:34
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