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Esteves Krasteva, Yana and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2008). Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation. In: "34th Annual Conference of the IEEE Industrial Electronics Society. IECON-2008", 10/11/2008-13/11/2008, Orlando, Florida, USA. ISBN 978-1-4244-1766-7. pp..
Title: | Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation |
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Author/s: |
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Item Type: | Presentation at Congress or Conference (Article) |
Event Title: | 34th Annual Conference of the IEEE Industrial Electronics Society. IECON-2008 |
Event Dates: | 10/11/2008-13/11/2008 |
Event Location: | Orlando, Florida, USA |
Title of Book: | Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE |
Date: | 2008 |
ISBN: | 978-1-4244-1766-7 |
Subjects: | |
Faculty: | E.T.S.I. Industriales (UPM) |
Department: | Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014] |
Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
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The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.
Item ID: | 3406 |
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DC Identifier: | https://oa.upm.es/3406/ |
OAI Identifier: | oai:oa.upm.es:3406 |
Official URL: | http://iecon2008.auburn.edu/index.html |
Deposited by: | Memoria Investigacion |
Deposited on: | 22 Jun 2010 08:51 |
Last Modified: | 20 Apr 2016 12:56 |