Accelerating the evolution of a systolic array-based evolvable hardware system

Abstract

Evolvable hardware is a type of hardware that is able to adapt to different problems by going through a previous training stage which uses an evolutionary algorithm to find an optimized configuration. This configuration can be achieved through dynamic partial reconfiguration of an FPGA. Having a short time for the training stage is critical for the system to be able to adapt to changing conditions in real time. However, one of the problems of evolvable hardware based on dynamic partial reconfiguration is its long evolution time, mostly due to its slow reconfiguration speed. This can make such systems unsuitable for applications which require adaptation in a few seconds. Nevertheless, different reconfiguration and evolution techniques can substantially reduce the time taken by an evolvable hardware system to evolve for a specific problem. In this article, a system initially able to evolve in 8 minutes is optimized using multiple techniques (reconfiguration methodology, evolutionary algorithm optimization, and parallelization) so that it is able to obtain similar results in less than 2 s, achieving a speedup of near 300 times. Extensive experimental results prove the benefits of such techniques.